cortex m0+: Fix bug doing read modify write on set only registers - #1006
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Kytezign wants to merge 1 commit into
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cortex m0+: Fix bug doing read modify write on set only registers#1006Kytezign wants to merge 1 commit into
Kytezign wants to merge 1 commit into
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This bug can be especially bad on the NVIC_ICER where a read, modify, write can actually disable all previously enabled interrupts (rather than just the intended interrupt)
Grazfather
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This bug can be especially bad on the NVIC_ICER where a read, modify, write can actually disable all previously enabled interrupts (rather than just the intended interrupt)
I'm not that familiar with the code base but I suspect this is an issue in other places. I might try to look closer later but I just wanted to get this out there as at least a partial fix for an issue I ran into earlier this year (and worked around at the time).
#955
Update to do write only rather than read, modify, write since 0 is meaningless and the read-back 1 may not have the desired effect.