spec: review ALU chips for redundancies and optimizations #638

After #624 changed the CPU to no longer ensure smaller-than-word input range checks, ALU chips needing these now have to enforce that individually.
Adding these checks directly in #624 has left some room for another pass through all chips to make sure this is done in a smart way and to make sure there are no further inconsistencies.
For instance:

• DVRM no longer needs to enforce the range-check on the MUL inputs
• LOAD is the only MSB8 consumer, and consumes multiple MSB8s, opening the door to either IS_BYTE-like batching, or replacing MSB8 entirely by MSB16.