Reverse engineering of the SONY PlayStation CPU (WIP)
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May 23, 2025 - C++
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standard-cells
Here are 30 public repositories matching this topic...
7 track standard cells for GF180MCU provided by GlobalFoundries.
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Dec 1, 2022 - Verilog
"High density" digital standard cells for SKY130 provided by SkyWater.
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Feb 22, 2023 - Verilog
9 track standard cells for GF180MCU provided by GlobalFoundries.
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Dec 5, 2022 - Verilog
This repository contains all major projects completed as part of the EECS 4612: Digital VLSI Design course at York University. The projects showcase the complete ASIC design flow — from RTL design to GDSII layout — using industry-grade tools like Cadence Genus, Innovus, and Virtuoso.
verilog semiconductor-physics genus custom-layout virtuoso digital-logic-design static-timing-analysis vlsi-design asic-design rtl-design innovus standard-cells eda-tools rtl-verification cmos-design rtl-to-gdsii cadence-tools
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Jul 12, 2025 - Verilog
Standard cell placement (global and detailed) tool based on modified algorithm “simulated annealing”
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Jan 7, 2026 - C++
"Low power" digital standard cells for SKY130 provided by SkyWater.
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Apr 23, 2021 - Verilog
"High speed" digital standard cells for SKY130 provided by SkyWater.
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Apr 23, 2021 - Verilog
"High density, low leakage" digital standard cells for SKY130 provided by SkyWater.
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Apr 23, 2021 - Verilog
"Low speed" digital standard cells for SKY130 provided by SkyWater.
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Apr 23, 2021 - Verilog
Standard cells for SKY90FD provided by SkyWater.
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Jul 28, 2022
"Medium speed" digital standard cells for SKY130 provided by SkyWater.
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Apr 23, 2021 - Verilog
"High voltage" digital standard cells for SKY130 provided by SkyWater.
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Apr 23, 2021 - Verilog
This repository exists to standardize how we define and reference standard cells across formats and toolchains. a) cell names and variants (logic families and aliases) b) drive strengths (X1, X2, ...) c) format emitters (Verilog, VHDL, SPICE, Spectre, CDL) d) topology and metadata used for consistent generation/verification.
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Apr 2, 2026 - Verilog
VLSI Design Project as part of Purdue's ECE559 Coursework
vlsi wallace-tree-multiplier cadence-virtuoso vlsi-physical-design vlsi-circuits cadence-spectre layout-design standard-cells hardware-engineering low-power-design integrated-media-solutions
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Jan 11, 2026 - Roff
Collection of functions to test standard cells
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Sep 8, 2025 - Jupyter Notebook
Research artifacts for the ICCAD 2026 paper “SAT-Based Free-Topology Transistor Network Synthesis under Stack-Height, Multi-Stage and Multi-Output Options.”
eda spice sat-solver vlsi sat iccad standard-cells circuit-synthesis iccad-2026 transistor-network-synthesis
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Sep 4, 2026 - SourcePawn
Python-based electronic design automation (EDA) tool for characterizing digital standard cells designed in SKY130 PDK. The characterization process is based in the Synopsys Liberty User Guides and Reference Manual Suite - Version 2017.06
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Nov 6, 2026 - Python
The fabricated CORDIC-1, rebuilt on a standard-cell library I designed myself: device physics, transistor sizing, cell layouts and ngspice-to-Liberty characterization all mine. Same RTL bit for bit, so the shuttle chip is the control group. On-die ring oscillators report my own cells' propagation delay in real silicon. Sky130 / TinyTapeout.
magic asic vlsi yosys semiconductor klayout ngspice cordic ring-oscillator static-timing-analysis openroad sky130 standard-cells tinytapeout open-source-silicon
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Aug 22, 2026 - Verilog
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