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    333 repositories

    • MAGIA

      Public
      Large-scale 2D mesh system with dedicated GeMM, on-chip RDMA and Rendez-vous accelerators.
      SystemVerilog
      •
      Apache License 2.0
      •12•33•22•3•Updated Nov 13, 2026Nov 13, 2026

    • magia-sdk

      Public
      C
      •
      Apache License 2.0
      •14•8•7•8•Updated Nov 13, 2026Nov 13, 2026

    • mempool

      Public
      A scalable 256/1024-RISC-V-core system with low-latency access into shared L1 memory.
      asicrisc-vmanycore
      asicrisc-vmanycore
      C
      •
      Apache License 2.0
      •62•333•3•6•Updated Nov 13, 2026Nov 13, 2026

    • croc

      Public
      A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
      asicriscvsystemverilog
      asicriscvsystemverilogrtl-design
      SystemVerilog
      •
      Other
      •144•295•3•9•Updated Nov 13, 2026Nov 13, 2026

    • Insitu-Cache

      Public
      SystemVerilog
      •
      Other
      •2•6•0•2•Updated Nov 13, 2026Nov 13, 2026

    • cheshire

      Public
      A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
      asicfpgasimulation
      asicfpgasimulationriscvsystemverilogrtl-design
      Verilog
      •
      Other
      •131•387•20•40•Updated Nov 13, 2026Nov 13, 2026

    • spatz

      Public
      Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
      C
      •
      Apache License 2.0
      •56•182•8•20•Updated Nov 13, 2026Nov 13, 2026

    • eda-benchmarks

      Public
      Shell
      •
      Other
      •0•13•0•0•Updated Nov 13, 2026Nov 13, 2026

    • axi

      Public
      AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
      asicfpgahardware
      asicfpgahardwarertlipsystemverilogaxinetwork-on-chipaxi4axi4-lite
      SystemVerilog
      •
      Other
      •381•1.8k•50•21•Updated Nov 12, 2026Nov 12, 2026

    • gwaihir

      Public
      aka Lago-Mio
      C
      •
      Other
      •5•8•8•10•Updated Nov 12, 2026Nov 12, 2026

    • obi

      Public
      OBI SystemVerilog synthesizable interconnect IPs for on-chip communication
      SystemVerilog
      •
      Other
      •16•27•3•10•Updated Nov 12, 2026Nov 12, 2026

    • ManyRVData

      Public
      This is the repository for CachePool architecture for the ManyRVData project
      C
      •
      Apache License 2.0
      •8•3•17•1•Updated Nov 12, 2026Nov 12, 2026

    • magia-kernels

      Public
      C
      •
      Apache License 2.0
      •0•0•0•0•Updated Nov 12, 2026Nov 12, 2026

    • bender

      Public
      A dependency management tool for hardware projects.
      Rust
      •
      Apache License 2.0
      •64•404•33•20•Updated Nov 12, 2026Nov 12, 2026

    • hci

      Public
      Heterogeneous Cluster Interconnect to bind special-purpose HW accelerators with general-purpose cluster cores
      SystemVerilog
      •
      Other
      •21•17•8•2•Updated Nov 11, 2026Nov 11, 2026

    • opope

      Public
      High frequency pipelined outer product
      SystemVerilog
      •
      Other
      •3•7•0•1•Updated Nov 11, 2026Nov 11, 2026

    • cluster_interconnect

      Public
      SystemVerilog
      •
      Other
      •17•18•1•2•Updated Nov 11, 2026Nov 11, 2026

    • memory_island

      Public
      An interleaved high-throughput low-contention L2 scratchpad memory.
      SystemVerilog
      •
      Other
      •7•6•5•4•Updated Nov 11, 2026Nov 11, 2026

    • redundancy_cells

      Public
      SystemVerilog IPs and Modules for architectural redundancy designs.
      SystemVerilog
      •
      Other
      •13•23•1•6•Updated Nov 11, 2026Nov 11, 2026

    • redmule

      Public
      GEMM and GEMM-Ops accelerator for PULP systems
      SystemVerilog
      •
      Other
      •29•126•4•5•Updated Nov 11, 2026Nov 11, 2026

    • DeepQuant

      Public
      A Python library for true quantization of neural networks
      Python
      •
      Apache License 2.0
      •7•9•1•4•Updated Nov 11, 2026Nov 11, 2026

    • datamover

      Public
      SystemVerilog
      •
      Other
      •2•2•3•1•Updated Nov 10, 2026Nov 10, 2026

    • spatz_vpu

      Public
      Spatz vector processing unit
      C
      •
      Apache License 2.0
      •11•2•1•8•Updated Nov 10, 2026Nov 10, 2026

    • cluster_icache

      Public
      An instruction cache for processor clusters, originally developed for the snitch cluster.
      SystemVerilog
      •
      Other
      •8•5•1•7•Updated Nov 10, 2026Nov 10, 2026

    • FlooNoC

      Public
      A Fast, Low-Overhead On-chip Network
      pythongeneratorsystemverilog
      pythongeneratorsystemverilognocaxi
      SystemVerilog
      •
      Apache License 2.0
      •84•372•26•10•Updated Nov 9, 2026Nov 9, 2026

    • cva6

      Public
      This is the fork of CVA6 intended for PULP development.
      Assembly
      •
      Other
      •1.1k•27•2•1•Updated Nov 8, 2026Nov 8, 2026

    • cvfpu

      Public
      Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
      SystemVerilog
      •
      Apache License 2.0
      •178•24•0•7•Updated Nov 6, 2026Nov 6, 2026

    • ace

      Public
      SystemVerilog
      •
      Other
      •7•27•0•1•Updated Nov 5, 2026Nov 5, 2026

    • clic

      Public
      RISC-V fast interrupt controller
      interruptrisc-vclic
      interruptrisc-vclic
      SystemVerilog
      •
      Apache License 2.0
      •5•35•7•5•Updated Nov 4, 2026Nov 4, 2026

    • MXCore

      Public
      Python
      •
      Apache License 2.0
      •2•3•0•0•Updated Nov 4, 2026Nov 4, 2026
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