feat: enable rvr execution of benchmarks#2753
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Claude finished @gdmlcjs's task in 3m 3s —— View job Code Review: PR #2753 — feat: enable rvr execution of benchmarks
Overall this is a clean, well-structured change that follows the existing patterns (AOT caching, feature-gated branches) closely. A few observations: Feature flag structure looks correctThe priority chain The Nits / suggestions
No issues found
Looks good to merge. |
Note: cells_used metrics omitted because CUDA tracegen does not expose unpadded trace heights. Commit: 0c3ad8c |
shuklaayush
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it's okay for now since we're going to remove aot later but i wonder if we can share more code between executor types. maybe we should have all executors conform to some trait interface
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Yes, that would be better. Should I add a ticket and merge? |
yes, let's do that |
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Claude finished @gdmlcjs's task in 1m 27s —— View job Code Review: PR #2753 — feat: enable rvr execution of benchmarks
Overall this is a solid, well-structured addition that mirrors the existing AOT benchmark patterns. The feature flag propagation to all extension circuit crates (the key fix) is correct, and the caching via Feature gate inconsistency in
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Enables running benchmarks through rvr extension. Benchmark tests do not check execution correctness and currently execution involving extensions other than RV32IM fail because
VmRvrExtensiontrait implementation is not properly wired.closes INT-7480