Cache-Aware Block-Transposed Chamfer/MaxSim Distance for f32#863
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Cache-Aware Block-Transposed Chamfer/MaxSim Distance for f32#863suri-kumkaran wants to merge 1 commit intomainfrom
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Codecov Report❌ Patch coverage is
Additional details and impacted files@@ Coverage Diff @@
## main #863 +/- ##
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- Coverage 89.33% 89.30% -0.04%
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Files 443 444 +1
Lines 83488 83548 +60
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+ Hits 74587 74614 +27
- Misses 8901 8934 +33
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What
A SIMD-accelerated MaxSim and Chamfer distance implementation for f32 multi-vector queries using block-transposed memory layout with L2/L1 cache-aware tiling.
New module:
diskann-quantization/src/multi_vector/distance/cache_aware/mod.rs—CacheAwareKernelunsafe trait + cache budget constantskernel.rs— generic 5-level tiling loop (tiled_reduce<K>)f32_kernel.rs— f32 SIMD micro-kernel (16×4 FMA),QueryBlockTransposedRefwrapper,MaxSim/Chamfertrait impls, testsSupporting changes:
block_transposed.rs— addedavailable_rows()andFrom<MatRef<Standard<T>>>distance/mod.rs,multi_vector/mod.rs— module wiring and re-exportsdistance/simple.rs— disambiguated a test callWhy
The existing simple kernel iterates query×doc in a flat nested loop, causing repeated cache evictions on large multi-vector workloads. By block-transposing the query and tiling both sides to fit in L2/L1, the new kernel keeps hot data resident and feeds the FMA pipeline more efficiently.
Design Decisions
CacheAwareKernelabstracts the micro-kernel so future element types (f16, i8/u8) reuse the tiling loop without duplication.QueryBlockTransposedRefnewtype: Prevents query/document argument swapping at compile time, analogous to the existingQueryMatRef.