[rstmgr,dv] Reset Manager DV ported to mocha#506
[rstmgr,dv] Reset Manager DV ported to mocha#506KolosKoblasz-Semify wants to merge 6 commits intolowRISC:mainfrom
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martin-velay
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| - files_rtl | ||
| - files_dv | ||
| default_tool: vcs | ||
| default_tool: xcelium |
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This is the source of your issue with the src file being not generated. The .src file is your file list generated from FuseSoc. I know that confusing, I went into this trap earlier too.
The VCS backend generates a .scr file, which is an identical format to a more standard .f format. We are only running FuseSoc up to the point it generates the filelist file (.scr in this case).
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| // Wait till rst_lc_n is inactive for non-aon. | ||
| `DV_WAIT(cfg.rstmgr_vif.resets_o.rst_lc_n[1]) | ||
| // Wait till rst_por_aon_n is inactive for non-aon. | ||
| `DV_WAIT(cfg.rstmgr_vif.resets_o.rst_por_aon_n[1]) |
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I think this should be the same reset as the one fed into the reset manager block in the top which is rst_por_io_n
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In rstmgr.sv line 351 constant zero is assigned to it:
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Probably makes sense to switch rst_*lc* with rst_por_io_n everywhere (and Marno agrees as well).
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Okay, but then it is DomainAonSel right?
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rst_lc_n[1] -> rst_por_io_n[1] so this is going to be Domain0Sel?
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Yes, DomainAonSel is 0, Domain0Sel is 1.
* open titan specific paths changed to mocha specific ones in the template files * 0001_Fix_Paths_And_Tools.patch file created with the changes Signed-off-by: Kolos Koblasz <kolos.koblasz@semify-eda.com>
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* The patched config and template config files added to the source code Signed-off-by: Kolos Koblasz <kolos.koblasz@semify-eda.com>
* 0002 patches fix the auto generated reset manager's dv files to be run Signed-off-by: Kolos Koblasz <kolos.koblasz@semify-eda.com>
* These modifications will enable to run block level simulations on rstmgr while using correct reset signals and domains in the UVM tb. Signed-off-by: Kolos Koblasz <kolos.koblasz@semify-eda.com>
* As result of previous patches to template files new dv files are generated for rstmgr. Signed-off-by: Kolos Koblasz <kolos.koblasz@semify-eda.com>
* rstmgr's smoketest added to top level simulation list Signed-off-by: Kolos Koblasz <kolos.koblasz@semify-eda.com>
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marnovandermaas
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Some comments from my end.
| - `CASCADED_ASSERTS(CascadeLcToLc, rst_lc_src_n[rstmgr_pkg::Domain0Sel], | ||
| - resets_o.rst_lc_n[rstmgr_pkg::Domain0Sel], SysCycles, clk_main_i) | ||
| - | ||
| - // Controlled by rst_sys_src_n. |
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There are a few resets controlled by SYS SRC in Mocha, such as rst_{main,io,spi_device,spi_host,i2c}_n
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It would be good to investigate whether we should have cascade asserts for those.
| else: | ||
| assert 0, "No preferred clock available" | ||
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| -preferred_rst_n = f"rst_lc_{preferred_domain}_n" |
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Can't we just update the preferred domain? This also fixes the power on reset preference below.
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TO DO
This PR will address: #433