[amdgcn] Add register-semantics scheduling graph and low-level scheduler option#512
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[amdgcn] Add register-semantics scheduling graph and low-level scheduler option#512
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Introduce RegisterSchedulerAttr, which extends the value scheduler graph with reaching-definition edges for InstOpInterface register ins and outs, after SSA and non-SSA (wait/barrier) edges. When building that graph, register-class memory effects on instructions are not treated as impurity for sync-point placement, so the scheduler matches post–ToRegisterSemantics DPS register semantics. Signed-off-by: Fabian Mora <fabian.mora-cordero@amd.com>
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Introduce RegisterSchedulerAttr, which extends the value scheduler graph with reaching-definition edges for InstOpInterface register ins and outs, after SSA and non-SSA (wait/barrier) edges. When building that graph, register-class memory effects on instructions are not treated as impurity for sync-point placement, so the scheduler matches post–ToRegisterSemantics DPS register semantics.