Skip to content

Actions: growly/bfg

Actions

All workflows

Actions

Loading...
Loading

Showing runs from all workflows
62 workflow runs
62 workflow runs

Filter by Workflow

⌥ + click/return to exclude

Filter by Event

⌥ + click/return to exclude

Filter by Status

⌥ + click/return to exclude

Filter by Branch

⌥ + click/return to exclude

Filter by Actor

⌥ + click/return to exclude
fix which D/Q ports are selected for scan chain in Sky130Interconnect… CI #62: Commit a4ae53e pushed by growly
7m 54s master
master
7m 54s
in transmission gate stack circuit, fix emitting ports before VPWR/VG… CI #61: Commit 9f46784 pushed by growly
6m 47s master
master
6m 47s
remove spurious "pin" layer objects in top-level cell causing false p… CI #60: Commit 435df50 pushed by growly
6m 11s master
master
6m 11s
fix spurious SCAN_OUT label causing LVS issues CI #59: Commit 6de7e1d pushed by growly
7m 27s master
master
7m 27s
leave a whole in psdm for polycon to address licon.9 CI #58: Commit 3a99b17 pushed by growly
7m 22s master
master
7m 22s
final clown shown CI #57: Commit be900bf pushed by growly
7m 23s master
master
7m 23s
i am a clown CI #56: Commit 2c196d3 pushed by growly
6m 6s master
master
6m 6s
minor parity flip CI #55: Commit 946c6b9 pushed by growly
6m 37s master
master
6m 37s
aaaaaaaargh CI #54: Commit e112ccc pushed by growly
7m 0s master
master
7m 0s
i need to sleep CI #53: Commit 7e05f69 pushed by growly
2m 25s master
master
2m 25s
netlist must reflect that muxes store INVERTED state for each gate; 0… CI #52: Commit eec20ae pushed by growly
6m 15s master
master
6m 15s
go to bed CI #51: Commit f7cd0e0 pushed by growly
7m 22s master
master
7m 22s
oops CI #50: Commit dbd542a pushed by growly
7m 40s master
master
7m 40s
add ability to size for encap at end of fingers; using fingers for mc… CI #49: Commit 3bd0e9d pushed by growly
7m 11s master
master
7m 11s
call the last flip flop output SCAN_OUT. put the pin in the right pla… CI #48: Commit 9377522 pushed by growly
6m 7s master
master
6m 7s
missing via.drawing disconnected clk input from clk bufs CI #47: Commit f646680 pushed by growly
6m 18s master
master
6m 18s
dfxtp: QI was never connected to Q_B CI #46: Commit a0a0b25 pushed by growly
7m 27s master
master
7m 27s
will lvs be less confused if we name the nets as it expects? CI #45: Commit 0b81364 pushed by growly
7m 20s master
master
7m 20s
Sky130TransmissionGate draws pmos_hvt so it should make the pmos_hvt … CI #44: Commit 37e6677 pushed by growly
7m 9s master
master
7m 9s
warn when circuit parameter are being silently squashed; add length/w… CI #43: Commit 7ec081c pushed by growly
7m 15s master
master
7m 15s
fix transmission gate stack ports CI #42: Commit 9d269be pushed by growly
6m 13s master
master
6m 13s
add ports for transmission gate stack CI #41: Commit e126e21 pushed by growly
6m 3s master
master
6m 3s
fix add comments to Sky130InterconnectMux2 to figure out wth i was do… CI #40: Commit 34a5063 pushed by growly
21m 31s master
master
21m 31s
Update README.md CI #39: Commit 7504ed4 pushed by growly
7m 41s master
master
7m 41s
Update README.md CI #38: Commit 1e580e2 pushed by growly
6m 17s master
master
6m 17s