Expand lane-crossing note in SIMD article with a worked example#54840
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tannergooding merged 2 commits intoJul 21, 2026
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Add a worked example under 'Cross-platform vectorization with Vector128' showing why lane-crossing operations (unlike element-wise ones) don't widen for free on x86/x64. Includes ASCII diagrams contrasting element-wise vs. pairwise combination and the Vector128 bit-layout / lower-upper split, plus a verified LaneCrossingExample.cs snippet demonstrating a correct Vector128 horizontal reduction, the naive (wrong) Vector256 extension, and the fix using GetLower/GetUpper. Co-authored-by: Copilot App <223556219+Copilot@users.noreply.github.com>
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Pull request overview
This PR expands the SIMD documentation to better explain why lane-crossing (pairwise/horizontal) operations don’t automatically benefit from widening vectors on x86/x64, by adding diagrams and a worked, verified C# example using Vector128<float> and Vector256<float>.
Changes:
- Adds ASCII diagrams and an explanatory subsection demonstrating how element-wise operations differ from lane-sensitive horizontal reductions on x86/x64.
- Introduces a new snippet (
LaneCrossingExample.cs) that contrasts a correctVector128<float>horizontal reduction with a naïveVector256<float>version and a corrected lane-bridging implementation. - Updates the snippet verification runner to execute and print the new example outputs when supported.
Show a summary per file
| File | Description |
|---|---|
| docs/standard/snippets/simd/csharp/Program.cs | Adds runtime-gated output for the new lane-crossing snippet methods in the verification runner. |
| docs/standard/snippets/simd/csharp/LaneCrossingExample.cs | New snippet showing correct and incorrect horizontal reduction patterns across 128-bit lanes on AVX. |
| docs/standard/simd.md | Expands the x86/x64 lane note into a worked example with diagrams and snippet references. |
Copilot's findings
- Files reviewed: 3/3 changed files
- Comments generated: 2
Split the Sse3/Avx gating in the verification runner so the Vector128 demo also runs on SSE3-only hardware without AVX. Add an explicit 'On x86/x64' lead-in where the worked example switches from the platform-neutral pairwise concept to the x86/x64-specific intrinsics. Co-authored-by: Copilot App <223556219+Copilot@users.noreply.github.com>
gewarren
approved these changes
Jul 20, 2026
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What
Expands the lane-crossing
[!NOTE]under "Cross-platform vectorization with Vector128" (added in #54834) into a worked example showing why lane-crossing operations don't widen for free on x86/x64, the way element-wise operations do.Content added
Add(same-index, width-agnostic) with a pairwise reduction (adjacent-index, width-sensitive).LaneCrossingExample.cs) with three methods:SumVector128: a correct two-roundSse3.HorizontalAddreduction onVector128<float>.SumVector256Naive: the same two-round pattern naively extended toVector256<float>-- compiles and runs, but only returns the lower lane's partial sum, not the full 8-element total, becauseAvx.HorizontalAddrepeats the pairwise pattern independently per 128-bit lane.SumVector256: the fix, bridging the lane boundary explicitly withGetLower/GetUpper.GetLower/GetUpperfix.Program.cs's verification runner.Verification
net11.0isn't available in this sandbox yet, so theLaneCrossingExample.cslogic was verified in an isolated scratch project targetingnet10.0:Numbers match the prose exactly (
[1,2,3,4,10,20,30,40]: lower lane sums to 10, upper lane to 100, naive gives only 10, fixed gives 110).Scope
Docs-only change to
docs/standard/simd.mdand theSimdSnippetssnippet project. No build/test infra changes. Out of scope (not included here): worked examples forWiden/Narrow/Shuffle, which the article currently only covers in the reference table.Internal previews