platform: xuantie: Add custom PMU device for cycle/instret OF#8
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This reverts commit bbd2d8a. Signed-off-by: Chen Pei <cp0613@linux.alibaba.com>
Sscofpmf does not define overflow interrupts for the fixed cycle and instret counters. XuanTie cores expose this via vendor mhpmevent0 (0x7E0) and mhpmevent2 (0x7E1), with the OF/INH bits split into mhpmevent0H (0x7E2) / mhpmevent2H (0x7E3) on RV32 -- mirroring the standard mhpmevent3/3H layout. mxstatus[8] (OFINT) is the per-hart master gate that lets the vendor OF bit raise lcofip. Instead of patching the generic sbi_pmu code path, register a sbi_pmu_device (mirroring the thead c9xx pattern) and layer the vendor OF handling on top of Sscofpmf via hw_counter_enable_irq / hw_counter_disable_irq. The hooks only act on ctr_idx 0 and 2; the programmable counters (ctr_idx >= 3) continue to use the standard Sscofpmf code path unchanged. On RV32 the OF bit is reached via mhpmevent0H/mhpmevent2H, matching what pmu_ctr_enable_irq_hw() does for mhpmevent3H+. Set mxstatus[8] (OFINT) in xuantie_early_init() outside the cold_boot guard so it is enabled per hart on every boot path. Wire it up via QUIRK_XUANTIE_PMU. The xuantie,dummy match enables it alongside the existing quirks, and a new xuantie,pmu compatible is provided for boards that need just this driver. Signed-off-by: Chen Pei <cp0613@linux.alibaba.com>
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