Search results

[WS5] RL-Kernel to vime integration and benchmark plan

Status: Open.

#158 In RL-Align/RL-Kernel;

· inaniloquentee opened on Jun 18, 2026

[Feat][Kernel] Fused CE LogProb without materializing logits + fused backward

Status: Open.

#155 In RL-Align/RL-Kernel;

· KJLdefeated opened on Jun 17, 2026

[WS1] dtype coverage in the numerical contract

feature

platform: cudaSpecific optimizations or bugs in NVIDIA graphics cards (such as FlashInfer, TMA optimizations)Specific optimizations or bugs in NVIDIA graphics cards (such as FlashInfer, TMA optimizations)

priority: highSevere congestion issues require the highest priority for resolution.Severe congestion issues require the highest priority for resolution.

sprint-0615

type: designIssues requiring in-depth discussion of architecture designIssues requiring in-depth discussion of architecture design

Status: Open.

#154 In RL-Align/RL-Kernel;

· Flink-ddd opened on Jun 17, 2026

[WS1] Backward-pass consistency across all ops

component: testingAdd test cases and benchmark-related tasksAdd test cases and benchmark-related tasks

feature

platform: cudaSpecific optimizations or bugs in NVIDIA graphics cards (such as FlashInfer, TMA optimizations)Specific optimizations or bugs in NVIDIA graphics cards (such as FlashInfer, TMA optimizations)

priority: highSevere congestion issues require the highest priority for resolution.Severe congestion issues require the highest priority for resolution.

sprint-0615

Status: Open.

#153 In RL-Align/RL-Kernel;

· Flink-ddd opened on Jun 17, 2026

[WS1] KV-cache path consistency (prefill & decode)

component: testingAdd test cases and benchmark-related tasksAdd test cases and benchmark-related tasks

feature

platform: cudaSpecific optimizations or bugs in NVIDIA graphics cards (such as FlashInfer, TMA optimizations)Specific optimizations or bugs in NVIDIA graphics cards (such as FlashInfer, TMA optimizations)

priority: highSevere congestion issues require the highest priority for resolution.Severe congestion issues require the highest priority for resolution.

sprint-0615

Status: Open.

#152 In RL-Align/RL-Kernel;

· Flink-ddd opened on Jun 17, 2026

[WS1][kernels] Batch-invariant embedding + LM head projection

component: kernelsTasks involving the development of CUDA and Triton underlying operatorsTasks involving the development of CUDA and Triton underlying operators

feature

platform: cudaSpecific optimizations or bugs in NVIDIA graphics cards (such as FlashInfer, TMA optimizations)Specific optimizations or bugs in NVIDIA graphics cards (such as FlashInfer, TMA optimizations)

priority: highSevere congestion issues require the highest priority for resolution.Severe congestion issues require the highest priority for resolution.

sprint-0615

Status: Open.

#151 In RL-Align/RL-Kernel;

· Flink-ddd opened on Jun 17, 2026

[WS1] Chain integration test (WS1 exit gate)

component: kernelsTasks involving the development of CUDA and Triton underlying operatorsTasks involving the development of CUDA and Triton underlying operators

feature

platform: cudaSpecific optimizations or bugs in NVIDIA graphics cards (such as FlashInfer, TMA optimizations)Specific optimizations or bugs in NVIDIA graphics cards (such as FlashInfer, TMA optimizations)

priority: highSevere congestion issues require the highest priority for resolution.Severe congestion issues require the highest priority for resolution.

sprint-0615

Status: Open.

#150 In RL-Align/RL-Kernel;

· Flink-ddd opened on Jun 17, 2026

[WS1] Batch-invariant elementwise / RoPE pass-through audit

component: kernelsTasks involving the development of CUDA and Triton underlying operatorsTasks involving the development of CUDA and Triton underlying operators

feature

platform: cudaSpecific optimizations or bugs in NVIDIA graphics cards (such as FlashInfer, TMA optimizations)Specific optimizations or bugs in NVIDIA graphics cards (such as FlashInfer, TMA optimizations)

priority: highSevere congestion issues require the highest priority for resolution.Severe congestion issues require the highest priority for resolution.

sprint-0615

Status: Open.

#149 In RL-Align/RL-Kernel;

· Flink-ddd opened on Jun 17, 2026

[WS1][kernels] Batch-invariant logprob (selected, locked reduction)

component: kernelsTasks involving the development of CUDA and Triton underlying operatorsTasks involving the development of CUDA and Triton underlying operators

feature

platform: cudaSpecific optimizations or bugs in NVIDIA graphics cards (such as FlashInfer, TMA optimizations)Specific optimizations or bugs in NVIDIA graphics cards (such as FlashInfer, TMA optimizations)

priority: highSevere congestion issues require the highest priority for resolution.Severe congestion issues require the highest priority for resolution.

sprint-0615

Status: Open.

#148 In RL-Align/RL-Kernel;

· Flink-ddd opened on Jun 17, 2026

[WS1][kernels] Batch-invariant attention (standard softmax)

component: kernelsTasks involving the development of CUDA and Triton underlying operatorsTasks involving the development of CUDA and Triton underlying operators

feature

platform: cudaSpecific optimizations or bugs in NVIDIA graphics cards (such as FlashInfer, TMA optimizations)Specific optimizations or bugs in NVIDIA graphics cards (such as FlashInfer, TMA optimizations)

priority: highSevere congestion issues require the highest priority for resolution.Severe congestion issues require the highest priority for resolution.

sprint-0615

Status: Open.

#147 In RL-Align/RL-Kernel;

· Flink-ddd opened on Jun 17, 2026

[WS1][kernels] Batch-invariant matmul / GEMM

component: kernelsTasks involving the development of CUDA and Triton underlying operatorsTasks involving the development of CUDA and Triton underlying operators

feature

platform: cudaSpecific optimizations or bugs in NVIDIA graphics cards (such as FlashInfer, TMA optimizations)Specific optimizations or bugs in NVIDIA graphics cards (such as FlashInfer, TMA optimizations)

priority: highSevere congestion issues require the highest priority for resolution.Severe congestion issues require the highest priority for resolution.

sprint-0615

Status: Open.

#146 In RL-Align/RL-Kernel;

· Flink-ddd opened on Jun 17, 2026

[WS1][kernels] Batch-invariant RMSNorm (forward + backward)

component: kernelsTasks involving the development of CUDA and Triton underlying operatorsTasks involving the development of CUDA and Triton underlying operators

feature

platform: cudaSpecific optimizations or bugs in NVIDIA graphics cards (such as FlashInfer, TMA optimizations)Specific optimizations or bugs in NVIDIA graphics cards (such as FlashInfer, TMA optimizations)

priority: highSevere congestion issues require the highest priority for resolution.Severe congestion issues require the highest priority for resolution.

sprint-0615

Status: Open.

#145 In RL-Align/RL-Kernel;

· Flink-ddd opened on Jun 17, 2026