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order - fuse - order kernel logic#74

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lkdvos merged 1 commit into
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fuse-order
Jul 15, 2026
Merged

order - fuse - order kernel logic#74
lkdvos merged 1 commit into
mainfrom
fuse-order

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@lkdvos

@lkdvos lkdvos commented Jul 14, 2026

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Closes #72.

The previous approach was fuse - order, where the fuse only works if at least one of the input arrays is ordered in increasing strides. The pathological case being permutedims(A, (2,1)) .= permutedims(B, (2, 1)), where fusion is trivial but never happened.

Here, I simply first order, then fuse, and then finally order again to make sure the leftover dim 1's from the fusion are migrated to the end.

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Codecov Report

✅ All modified and coverable lines are covered by tests.

Files with missing lines Coverage Δ
src/broadcast.jl 83.33% <100.00%> (ø)
src/mapreduce.jl 81.63% <100.00%> (+0.23%) ⬆️
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@lkdvos lkdvos enabled auto-merge (squash) July 15, 2026 00:10
@lkdvos lkdvos requested a review from Jutho July 15, 2026 00:11
Comment thread src/mapreduce.jl
Comment on lines +118 to +122
g = 8 * sizeof(Int) - leading_zeros(M + 1)
importance = 2 .* (1 .<< (g .* (N .- indexorder(strides[1]))))
for k in 2:M
importance = importance .+ (1 .<< (g .* (N .- indexorder(strides[k]))))
end

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I have to admit that I forgot exactly how this cost model works 😄

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Something like, the importance of a dimension is

sum over arrays of 2^(log2(M+2) * (N - indexorder of dimension in array))

So if an index is the first index in each of the arrays, its importance is

(M+1) * (M+2)^((N-1))

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I also didn't really look into this in detail. I think realistically, any stride that goes beyond 2 cacheline widths probably doesn't actually matter all that much, so the main part is that we want as many contiguous writes and then contiguous reads?

To be totally honest, I was looking at the permutation part of this last week and since I have a machine with 512b SIMD registers, it's actually possible to speed up this kernel by quite a lot by doing an in-register transpose, for example reading in 8 lanes of 8 contiguous Float64s, then SIMD shuffling them so they're transposed, and then writing the 8 lanes of 8 contiguous floats. The Julia compiler does not seem to be autovectorizing this.

The caveat is of course that you need 2 stride-1 dimensions that are large enough, the exact kernel sizes have to be tuned for the machines, and that this works mainly for larger SIMD widths, as the benefit decreases for larger eltypes or smaller lanewidths.

Anyways, might at some point try and include such a kernel, but probably don't want to do this in Julia, that seems a compile-time nightmare :)

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Oh yes, the strided kernels are far from optimal, especially for very specific tasks like transpose. At some point I wanted to invest time to use LoopVectorization for writing a dedicated add_transpose implementation, but never got to it. Given the current states of LoopVectorization, it might not have been the best idea anyway.

Comment thread src/mapreduce.jl
@lkdvos lkdvos merged commit 9f03366 into main Jul 15, 2026
10 of 13 checks passed
@lkdvos lkdvos deleted the fuse-order branch July 15, 2026 08:32
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perf: threading unused for permuted contiguous views

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