diff --git a/pyproject.toml b/pyproject.toml index efaa4734a..7b7631dae 100644 --- a/pyproject.toml +++ b/pyproject.toml @@ -26,7 +26,7 @@ keywords = [ [tool.poetry.dependencies] python = "^3.10" -capstone = "^5" +capstone = ">=5,<7" unicorn = "2.1.3" pefile = ">=2022.5.30" python-registry = "^1.3.1" diff --git a/qiling/arch/arm64.py b/qiling/arch/arm64.py index f3b634800..2965d9c82 100644 --- a/qiling/arch/arm64.py +++ b/qiling/arch/arm64.py @@ -7,7 +7,10 @@ from typing import Optional from unicorn import Uc, UC_ARCH_ARM64, UC_MODE_ARM -from capstone import Cs, CS_ARCH_ARM64, CS_MODE_ARM +try: + from capstone import Cs, CS_ARCH_AARCH64 as CS_ARCH_ARM64, CS_MODE_ARM +except ImportError: + from capstone import Cs, CS_ARCH_ARM64, CS_MODE_ARM from keystone import Ks, KS_ARCH_ARM64, KS_MODE_ARM from qiling import Qiling diff --git a/qiling/arch/riscv.py b/qiling/arch/riscv.py index 51b09113d..afa768e5b 100644 --- a/qiling/arch/riscv.py +++ b/qiling/arch/riscv.py @@ -56,11 +56,14 @@ def endian(self) -> QL_ENDIAN: @cached_property def disassembler(self) -> Cs: try: - from capstone import CS_ARCH_RISCV, CS_MODE_RISCV32, CS_MODE_RISCVC + from capstone import CS_ARCH_RISCV, CS_MODE_RISCV32 except ImportError: raise QlErrorNotImplemented("Capstone does not yet support riscv, upgrade to capstone 5.0") - else: - return Cs(CS_ARCH_RISCV, CS_MODE_RISCV32 + CS_MODE_RISCVC) + try: + from capstone import CS_MODE_RISCV_C as CS_MODE_RISCVC + except ImportError: + from capstone import CS_MODE_RISCVC + return Cs(CS_ARCH_RISCV, CS_MODE_RISCV32 + CS_MODE_RISCVC) @cached_property def assembler(self) -> Ks: diff --git a/qiling/arch/riscv64.py b/qiling/arch/riscv64.py index 036ab2aff..1b669d636 100644 --- a/qiling/arch/riscv64.py +++ b/qiling/arch/riscv64.py @@ -38,11 +38,14 @@ def uc(self) -> Uc: @cached_property def disassembler(self) -> Cs: try: - from capstone import CS_ARCH_RISCV, CS_MODE_RISCV64, CS_MODE_RISCVC + from capstone import CS_ARCH_RISCV, CS_MODE_RISCV64 except ImportError: raise QlErrorNotImplemented("Capstone does not yet support riscv, upgrade to capstone 5.0") - else: - return Cs(CS_ARCH_RISCV, CS_MODE_RISCV64 + CS_MODE_RISCVC) + try: + from capstone import CS_MODE_RISCV_C as CS_MODE_RISCVC + except ImportError: + from capstone import CS_MODE_RISCVC + return Cs(CS_ARCH_RISCV, CS_MODE_RISCV64 + CS_MODE_RISCVC) @cached_property def assembler(self) -> Ks: