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Frontend', slug: 'architecture/frontend/descriptor' }, + ], + }, + { label: 'Midend', slug: 'architecture/midend' }, + { label: 'Backend', slug: 'architecture/backend' }, + ], + }, + { + label: 'Guides', + items: [ + { label: 'Quickstart', slug: 'guides/quickstart' }, + { label: 'System Integration', slug: 'guides/system-integration' }, + { label: 'Error Handling', slug: 'guides/error-handling' }, + { label: 'Verification', slug: 'guides/verification' }, + { label: 'Performance and Limitations', slug: 'guides/performance-limitations' }, + { label: 'Docs Verification Plan', slug: 'guides/docs-verification' }, + ], + }, + ], + }), + ], +}); diff --git a/doc/site/package-lock.json b/doc/site/package-lock.json new file mode 100644 index 00000000..49d22bf9 --- /dev/null +++ b/doc/site/package-lock.json @@ -0,0 +1,7421 @@ +{ + "name": "idma-docs", + "version": "0.0.1", + "lockfileVersion": 3, + "requires": true, + "packages": { + "": { + "name": "idma-docs", + "version": "0.0.1", + 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mode 100644 index 00000000..be6eb1ba --- /dev/null +++ b/doc/site/public/fig/architecture_overview.svg @@ -0,0 +1,27 @@ + + + + + + + + + + + + +iDMA Architecture Overview +Frontend +Register IF / DescriptorsSnitch ISA +Midend +N-D decomposition(optional) +Backend +Legalizer → R/WTransport Layer +idma_req_t +idma_req_t +idma_rsp_t +idma_rsp_t +PlatformInterface +AXI4OBIAXI StreamINIT + + \ No newline at end of file diff --git a/doc/site/public/fig/backend.svg b/doc/site/public/fig/backend.svg new file mode 100644 index 00000000..9e08f3b6 --- /dev/null +++ b/doc/site/public/fig/backend.svg @@ -0,0 +1,72 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +iDMA Backend +Legalizer +Transport Layer +BurstSplitter +Error FSM +tx +tx +retire +retire +ReadModule +Buffer +WriteModule +1D request +response +error handling +AR +R +AW +B +W + + \ No newline at end of file diff --git a/doc/site/public/fig/iDMA_overview.svg b/doc/site/public/fig/iDMA_overview.svg new file mode 100644 index 00000000..f8f4f482 --- /dev/null +++ b/doc/site/public/fig/iDMA_overview.svg @@ -0,0 +1,3 @@ + + +
response
response
Backend
Backend
request
request
error
error
response
response
Midend
Midend
request
request
error
error
Frontend
Frontend
interface
interface
AXI
AXIViewer does not support full SVG 1.1 \ No newline at end of file diff --git a/doc/site/public/fig/legalizer.svg b/doc/site/public/fig/legalizer.svg new file mode 100644 index 00000000..6e2a61f5 --- /dev/null +++ b/doc/site/public/fig/legalizer.svg @@ -0,0 +1,48 @@ + + + + + + + + + + + + + + + + + +Legalizer +Splits 1D transfers into protocol-legal bursts +idma_req_t +src_addr dst_addr length protocol options +Example: 6 KB transfer starting at 0x0C00 (3 KB into a 4 KB page) +Burst 11 KB +Burst 24 KB +Burst 31 KB +0x1000 +0x2000 +0x0C00 +0x2400 +4 KB page boundaries (AXI) +Page size per protocol: +AXI 4 KBOBI 1 word (no bursts)TileLink POW2 aligned +Read / Write synchronization +Coupled (default) +Both paths split at whicheverpage boundary comes first.Used when both protocols burst. +Decoupled +Read and write advance at theirown pace. Required when one sidehas no burst support (e.g. OBI). +Per-burst output (emitted each cycle until transfer complete) +Read Request +Protocol metadata (AR) addr, len, size, burst, idDatapath control offset, shift, is_single +Write Request +Protocol metadata (AW) addr, len, size, burst, idDatapath control offset, shift, num_beats last, super_last +idma_r_req_t +idma_w_req_t +Advanceaddr,reducelength +Iterates one burst per cycle. last flag marks the final burst of the transfer. + + \ No newline at end of file diff --git a/doc/site/public/fig/system_integration.svg b/doc/site/public/fig/system_integration.svg new file mode 100644 index 00000000..22e20d0d --- /dev/null +++ b/doc/site/public/fig/system_integration.svg @@ -0,0 +1,46 @@ + + + + + + + + + + + + + + + + + + + + +iDMA System Integration +Typical configuration: Register Frontend (64-bit 2D) + ND Midend + AXI Backend +RegisterFrontend +idma_reg64_2d_top +NDMidend +idma_nd_midend +Backend +idma_backend_rw_axi +Transfer ID Gen +CPURegBus +AXIFabric +reg_req/rsp +idma_nd_req_t +idma_rsp_t +idma_req_t +idma_rsp_t +AR / R +AW / W / B +next_id +done_id +issue / retire +busy_o → busy_i +Key parameters: DataWidth AddrWidth NumAxInFlight BufferDepth(≥3) ErrorCap +Type macros: `IDMA_TYPEDEF_REQ_T `IDMA_TYPEDEF_RSP_T `AXI_TYPEDEF_REQ_T + + \ No newline at end of file diff --git a/doc/site/public/fig/system_integration_alt.svg b/doc/site/public/fig/system_integration_alt.svg new file mode 100644 index 00000000..04bf2348 --- /dev/null +++ b/doc/site/public/fig/system_integration_alt.svg @@ -0,0 +1,56 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + +iDMA Frontend Integration Variants +Descriptor Frontend (CVA6 / Linux) +CPU(CVA6) +DescriptorFrontend +idma_desc64_top +Backend +AXIFabric +Descriptor Memory +reg_req/rsp +AXI master +idma_req_t +idma_rsp_t +AR / R +AW / W / B +irq_o +Snitch ISA Frontend (tightly coupled) +SnitchCore +idma_inst64_top +ND Midend +Backend +×N +AXIFabric +acc_req_t +acc_res_t +axi_req/rsp [N] +hart_id_i • events_o • busy_o[N] +desc64: Separate backend — descriptors fetched from memory via AXI master, IRQ on completion +inst64: Self-contained — backend + 2D midend instantiated internally, driven by Snitch ISA instructions + + \ No newline at end of file diff --git a/doc/site/public/fig/variant_matrix.svg b/doc/site/public/fig/variant_matrix.svg new file mode 100644 index 00000000..312cce98 --- /dev/null +++ b/doc/site/public/fig/variant_matrix.svg @@ -0,0 +1,49 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +iDMA Backend Variants +Write Protocol(s) +ReadProtocol +AXI4 +OBI +AXI4 +AXI Stream +AXI4 +INIT +OBI +INIT +AXI4 +OBI +rw_axi +r_axi_w_obi +rw_axi_rw_axis +r_axi_rw_init_rw_obi +r_obi_w_axi +r_obi_rw_init_w_axi +Base variants +Occamy variants +Naming: r_<read>_w_<write> • rw = same protocol for both • Extend via IDMA_ADD_IDS + + \ No newline at end of file diff --git a/doc/site/src/content.config.ts b/doc/site/src/content.config.ts new file mode 100644 index 00000000..90bcd412 --- /dev/null +++ b/doc/site/src/content.config.ts @@ -0,0 +1,13 @@ +// Copyright 2025 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 + +// Authors: +// - Daniel Keller + +import { defineCollection } from 'astro:content'; +import { docsSchema } from '@astrojs/starlight/schema'; + +export const collections = { + docs: defineCollection({ schema: docsSchema() }), +}; diff --git a/doc/site/src/content/docs/architecture/backend.md b/doc/site/src/content/docs/architecture/backend.md new file mode 100644 index 00000000..11516d39 --- /dev/null +++ b/doc/site/src/content/docs/architecture/backend.md @@ -0,0 +1,164 @@ +--- +title: Backend +description: The backend executes 1D transfers over concrete transport protocols. +--- + +## Backend Role + +The backend is the lowest layer of the iDMA pipeline. It takes 1D transfer requests from the midend and drives the actual bus transactions. Each backend variant targets a specific combination of read and write protocols. Generated modules follow the naming pattern `idma_backend_` (e.g., `idma_backend_rw_axi`, `idma_backend_r_obi_w_axi`). + +![Backend Architecture](/fig/backend.svg) + +### Transfer Lifecycle + +When a 1D transfer request arrives at the backend, it flows through three stages. First, the **legalizer** splits the request into protocol-legal bus bursts (bursts that don't cross page boundaries or exceed the protocol's maximum beat count) — respecting page boundaries, maximum burst lengths, and alignment constraints. Each burst produces a set of control signals (offset, tailer, shift) that describe how the data needs to be realigned. Second, the **transport layer** executes each burst: the read channel fetches data from the source, barrel shifters realign byte lanes, the data buffer absorbs timing differences, and the write channel stores data at the destination. Third, the **error handler** (if enabled) monitors bus responses and reports faults to software. The backend signals completion through `idma_rsp_t` once all bursts of a transfer have finished. + +## Parameters + +The most important parameters for a new integration are `DataWidth` (match your bus width), `BufferDepth` (use 3 unless area-constrained), and `HardwareLegalizer` (use 1 unless your software pre-splits bursts). The remaining parameters tune throughput and area — see the [parameter presets](../guides/system-integration/#4-set-parameters) in the System Integration guide for recommended combinations. + +| Parameter | Default | Description | +|-----------|---------|-------------| +| `DataWidth` | 16 | Data bus width in bits. Must be a power of 2 in {16, 32, 64, 128, 256, 512, 1024} | +| `AddrWidth` | 24 | Address width in bits. Must be >= 12 | +| `UserWidth` | 1 | AXI user signal width. Must be > 0 | +| `AxiIdWidth` | 1 | AXI ID width. Must be > 0 | +| `NumAxInFlight` | 2 | Number of concurrent in-flight transactions. Must be > 1 | +| `BufferDepth` | 2 | Depth of the internal reorder buffer. 2 = minimal, **3 = recommended** because depth-2 buffers stall on misaligned transfers where read and write offsets differ, requiring an extra buffer slot for the alignment pipeline | +| `TFLenWidth` | 24 | Transfer length width. Max transfer size is `2^TFLenWidth` bytes. Must be >= 12 and <= AddrWidth | +| `MemSysDepth` | 0 | Depth of the attached memory system (additional pipeline stages) | +| `CombinedShifter` | 0 | Use a single barrel shifter instead of two (saves area, data no longer word-aligned in buffer) | +| `RAWCouplingAvail` | 1 | Enable R-AW coupling hardware. Should be 1 for pure AXI-to-AXI variants (`rw_axi`); set to 0 for mixed-protocol variants where the write protocol has no AW channel | +| `MaskInvalidData` | 1 | Zero out invalid bytes on the manager interface to reduce toggling | +| `HardwareLegalizer` | 1 | Include hardware burst legalization. If 0, software must ensure legal bursts | +| `RejectZeroTransfers` | 1 | Reject zero-length transfers with a `BACKEND` error response | +| `ErrorCap` | `NO_ERROR_HANDLING` | Error handling capability: `NO_ERROR_HANDLING` or `ERROR_HANDLING` | +| `PrintFifoInfo` | 0 | Print FIFO configuration during elaboration | + +The maximum number of transfers in-flight at any point is: + +``` +MetaFifoDepth = BufferDepth + NumAxInFlight + MemSysDepth +``` + +This determines how many 1D bursts can be in-flight simultaneously — `BufferDepth` entries in the data buffer, `NumAxInFlight` transactions on the bus, and `MemSysDepth` stages in the external memory system. + +## Interface + +### Port Groups + +All backends have the Request, Response, Bus Read, Bus Write, and Busy port groups. The Error Handler ports are only present when `ErrorCap = ERROR_HANDLING`. + +| Group | Signals | Direction | Description | +|-------|---------|-----------|-------------| +| **Request** | `idma_req_i`, `req_valid_i`, `req_ready_o` | in/in/out | 1D transfer request (valid/ready handshake) | +| **Response** | `idma_rsp_o`, `rsp_valid_o`, `rsp_ready_i` | out/out/in | Transfer completion response | +| **Error Handler** | `idma_eh_req_i`, `eh_req_valid_i`, `eh_req_ready_o` | in/in/out | Error handling action (CONTINUE/ABORT) | +| **Bus Read** | `_read_req_o`, `_read_rsp_i` | out/in | Read channel to memory system | +| **Bus Write** | `_write_req_o`, `_write_rsp_i` | out/in | Write channel to memory system | +| **Busy** | `busy_o` | out | Per-subunit busy flags (`idma_busy_t`) | + +### Busy Signal (`idma_busy_t`) + +Software can poll the busy signal to check if the backend is idle before clock-gating, resetting, or reconfiguring it. Each flag corresponds to a specific subunit — if a transfer stalls, the stuck flag identifies the bottleneck: + +```verilog +typedef struct packed { + logic buffer_busy; // Data buffer contains valid data + logic r_dp_busy; // Read datapath active + logic w_dp_busy; // Write datapath active + logic r_leg_busy; // Read legalizer processing + logic w_leg_busy; // Write legalizer processing + logic eh_fsm_busy; // Error handler FSM not idle + logic eh_cnt_busy; // Outstanding transfer counter != 0 + logic raw_coupler_busy; // R-AW coupler holds pending AWs +} idma_busy_t; +``` + +## Variant Matrix + +Each backend variant combines a set of read and write protocols: + +| Variant ID | Read Protocol | Write Protocol | +|------------|---------------|----------------| +| `rw_axi` | AXI4 | AXI4 | +| `r_obi_w_axi` | OBI | AXI4 | +| `r_axi_w_obi` | AXI4 | OBI | +| `rw_axi_rw_axis` | AXI4 | AXI4 + AXI Stream | +| `r_obi_rw_init_w_axi` | OBI | INIT + AXI4 | +| `r_axi_rw_init_rw_obi` | AXI4 | INIT + OBI | + +![Variant Matrix](/fig/variant_matrix.svg) + +## Legalizer + +The legalizer decomposes a 1D transfer request into a sequence of protocol-legal bus bursts. It operates as two coupled state machines — one for the read side, one for the write side — that track the remaining bytes and current address of each transfer independently. + +The legalizer is pure control path: it does not touch the data. It computes page/burst boundaries, splits transfers accordingly, and emits `offset`, `tailer`, and `shift` values that the transport layer uses for data realignment. + +![Legalizer](/fig/legalizer.svg) + +### Splitting Rules + +| Protocol | Burst Mode | Page Size | Max Beats | +|----------|-----------|-----------|-----------| +| AXI | `split_at_page_boundary` | 4096 B | 256 | +| TileLink | `only_pow2` | 2048 B | Power-of-2 sized | +| OBI | `not_supported` (single-beat) | StrbWidth | 1 | +| INIT | `not_supported` (single-beat) | StrbWidth | 1 | +| AXI Stream | `not_supported` (single-beat) | StrbWidth | 1 | + +For AXI, the legalizer ensures bursts do not cross 4 KiB page boundaries and respect the 256-beat maximum. TileLink uses power-of-2 aligned bursts with a 2048 B page size (limited by the TLToAXI4 bridge for AXI compliance); in TLToAXI4 compatibility mode, write bursts are further limited to 32 beats and never cross page boundaries. For non-bursting protocols (OBI, INIT, AXI Stream), each transfer is a single bus-width beat. The effective page size is `min(max_beats * StrbWidth, page_size)`. + +If `HardwareLegalizer=1` and software submits a transfer crossing a page boundary, the legalizer splits it automatically. With `HardwareLegalizer=0`, such a transfer would violate the protocol and cause undefined bus behavior. + +**Example**: A 5000-byte AXI transfer starting at address `0xFF8`. The 4 KiB page boundary is at `0x1000`, only 8 bytes away. The legalizer emits: burst 1 (8 bytes at `0xFF8` — reaches page boundary), burst 2 (4096 bytes at `0x1000`), burst 3 (896 bytes at `0x2000`). Each burst stays within a single 4 KiB page and respects the 256-beat limit. + +### Datapath Control Signals + +The legalizer communicates with the transport layer through internal control signals (`offset`, `tailer`, `shift`, `is_single`) that describe how each burst should be realigned. These are not visible to software — they flow through decoupling FIFOs between the two stages. + +### Software Legalization + +When `HardwareLegalizer=0`, the legalizer is bypassed and replaced with a simple `stream_fork` that synchronizes the read and write paths. In this mode, software is responsible for ensuring all transfers are already legal for the target protocol (e.g., no AXI page-boundary crossings). Use this only when software pre-splits all transfers into protocol-legal bursts (e.g., an RTOS DMA driver that already handles AXI page boundaries). This saves ~1–2K gates but moves burst-splitting responsibility to the driver. + +## Transport Layer + +### Architecture + +The transport layer is responsible for moving data from source to destination, handling the byte-lane realignment that arises when source and destination addresses have different bus-word offsets. It contains the read channel, byte-granular data buffer, and write channel. Data flows as: **read port** -> **read barrel shifter** -> **dataflow element (buffer)** -> **write barrel shifter** -> **write port**. + +The buffer (`idma_dataflow_element`) is an array of independent FIFOs, one per byte lane (`StrbWidth` = `DataWidth / 8`, i.e., the number of byte lanes; `StrbWidth` FIFOs of depth `BufferDepth`). This byte-granular design allows data to enter and leave the buffer at arbitrary byte-lane positions, enabling misaligned transfers without additional alignment stages. + +### Data Realignment + +:::note[Figure placeholder] +Diagram: data realignment through read shifter, buffer, and write shifter. +Show an example with misaligned source/destination offsets and byte lane rotation. +::: + +Two barrel shifters handle the address offset difference between source and destination. The **read shifter** aligns incoming data based on the source address offset; the **write shifter** rotates data to match the destination address offset. + +When `CombinedShifter=1`, both shifts are folded into a single operation before the buffer. This halves the shifter area but means data inside the buffer is no longer word-aligned. The tradeoff is area (single shifter) vs. timing (data alignment happens earlier in the pipeline). + +## Channel Coupler + +The R-AW channel coupler (`idma_channel_coupler`) holds back AW requests until the first corresponding R beat arrives. Without coupling, the DMA could issue a write address before the read data arrives, which wastes write-side resources and can increase interconnect pressure — particularly problematic in shared-bus fabrics. With coupling enabled, the write address is only sent once data is available, preventing write-before-read ordering hazards. Controlled by `RAWCouplingAvail` (enables the hardware) and `decouple_aw` (per-transfer opt-in via `backend_options_t`). Only available for AXI-to-AXI variants. + +Despite the name, `decouple_aw` actually *enables* R-AW coupling (holding AW until R data arrives). The name refers to the backend option struct field (`beo.decouple_aw`), where setting it to 1 activates the coupling logic. + +**When coupling helps**: On a shared AXI bus, an uncoupled DMA issues AW immediately, occupying a write-side slot before data is available. With coupling, AW waits for the first R beat, ensuring the write port is only claimed when data is ready to flow. **When to disable**: If the read and write ports go to different memory controllers (no shared resources), coupling adds unnecessary latency. + +## Error Handler + +The error handler monitors R and W datapath responses for non-OKAY AXI responses. When an error is detected, it reports the faulting burst address and error type to software and waits for a CONTINUE or ABORT action. See the [Error Handling guide](../guides/error-handling/) for the full FSM description and software handling patterns. + +## Source Files + +- **Backend template**: `src/backend/tpl/idma_backend.sv.tpl` +- **Legalizer template**: `src/backend/tpl/idma_legalizer.sv.tpl` +- **Transport layer template**: `src/backend/tpl/idma_transport_layer.sv.tpl` +- **Error handler**: `src/backend/idma_error_handler.sv` +- **Channel coupler**: `src/backend/idma_channel_coupler.sv` +- **Dataflow element**: `src/backend/idma_dataflow_element.sv` +- **Generated output**: `target/rtl/idma_backend_*.sv` diff --git a/doc/site/src/content/docs/architecture/frontend/descriptor.md b/doc/site/src/content/docs/architecture/frontend/descriptor.md new file mode 100644 index 00000000..be4721b3 --- /dev/null +++ b/doc/site/src/content/docs/architecture/frontend/descriptor.md @@ -0,0 +1,107 @@ +--- +title: Descriptor Frontend +description: Descriptor-ring frontend for hardware-managed transfer queues. +--- + +## Descriptor Frontend Role + +The descriptor frontend (`idma_desc64_top`) uses a linked list of transfer descriptors in shared memory. Hardware fetches descriptors autonomously over an AXI read port, enabling software to enqueue multiple transfers without polling for completion of each one. + +## Descriptor Format + +The descriptor frontend's reshaper (a module that converts the descriptor's flag bits into the `idma_req_t` option fields, `idma_desc64_reshaper`) maps flag bits to backend options, but also hardcodes some values. Notably, `src_max_llen` and `dst_max_llen` are always set to 0 (full debursting: every transfer is broken into single-beat bus transactions, maximum protocol compliance at the cost of throughput), and `lock`, `prot`, `qos`, `region` are zeroed. These options cannot be controlled per-descriptor. + +Each descriptor is a 256-bit packed struct stored in shared memory. In a SystemVerilog packed struct, the first field (`flags`) occupies the most-significant bits and the last field (`dest_addr`) occupies the least-significant bits. In memory (little-endian), `dest_addr` is at the lowest byte address: + +```verilog +typedef struct packed { + logic [31:0] flags; // Transfer flags (see below) + logic [31:0] length; // Transfer length in bytes + addr_t next; // Address of next descriptor (0xFFFF...F = end of chain) + addr_t src_addr; // Source address + addr_t dest_addr; // Destination address +} descriptor_t; // Total: 256 bits (addr_t = 64 bits) +``` + +Descriptors must be in memory accessible to the DMA's AXI read port. Descriptors are read as 256-bit naturally-aligned bursts. + +:::caution[Cache coherency] +If the CPU uses a data cache, descriptors must be in an uncached or cache-coherent memory region. If you modify a descriptor after writing it and before the DMA reads it, flush the relevant cache lines. The DMA does not snoop CPU caches. +::: + +### Flags Bitfield + +| Bits | Field | Description | +|------|-------|-------------| +| 0 | `irq` | Trigger interrupt on completion | +| 2:1 | `src_burst` | Source burst type: 00=FIXED, 01=INCR, 10=WRAP | +| 4:3 | `dst_burst` | Destination burst type: 00=FIXED, 01=INCR, 10=WRAP | +| 5 | `decouple_rw` | Fully decouple read and write channels — the backend can write without waiting for reads to complete (risk of deadlock if buffer fills) | +| 6 | `decouple_aw` | Safer decoupling: write *addresses* are held back until the first read data arrives, but once data starts flowing, reads and writes proceed independently | +| 7 | `reduce_len` | Reduce burst length on both source and destination (`opt.beo.src_reduce_len` + `opt.beo.dst_reduce_len`) | +| 11:8 | `src_cache` | AXI cache attributes for source (bufferable, modifiable, read-alloc, write-alloc) | +| 15:12 | `dst_cache` | AXI cache attributes for destination | +| 23:16 | `axi_id` | AXI ID for the transfer | +| 31:24 | — | Reserved | + +**Typical flags values**: `0x00000000` — default (INCR burst, no decoupling, no IRQ). `0x00000001` — IRQ on completion. `0x00000061` — decouple_aw + decouple_rw + IRQ. + +## Descriptor Chain Example + +:::note[Figure placeholder] +Diagram: descriptor chain layout in memory. +Show two descriptors, next pointer, and end-of-chain marker. +::: + +A two-descriptor chain that transfers 64 bytes, then 128 bytes, then stops. Assume the descriptors are allocated at addresses `0x4000` and `0x4020` (32 bytes apart, naturally aligned): + +``` +// Descriptor at address 0x4000: +// src_addr = 0x1000 +// dest_addr = 0x2000 +// next = 0x4020 (address of the second descriptor) +// length = 64 +// flags = 0x00000000 (no IRQ, INCR burst, no decoupling) + +// Descriptor at address 0x4020: +// src_addr = 0x1100 +// dest_addr = 0x2100 +// next = 0xFFFFFFFF_FFFFFFFF (end of chain) +// length = 128 +// flags = 0x00000001 (IRQ on completion) +``` + +## Parameters + +The descriptor frontend is configured through module parameters at instantiation time: + +| Parameter | Default | Description | +|-----------|---------|-------------| +| `AddrWidth` | 64 | Address width | +| `DataWidth` | 64 | AXI data width | +| `AxiIdWidth` | 3 | AXI ID width | +| `InputFifoDepth` | 8 | Depth of the descriptor address input FIFO | +| `PendingFifoDepth` | 8 | Depth of the pending request tracking FIFO | +| `BackendDepth` | 0 | Backend pipeline depth (`NumAxInFlight + BufferDepth`) | +| `NSpeculation` | 4 | Number of descriptors to prefetch speculatively | + +## Programming Sequence + +1. **Allocate descriptors** in memory accessible to both CPU and DMA (e.g., uncached or coherent region) +2. **Fill descriptor fields**: Set `src_addr`, `dest_addr`, `length`, `flags` for each transfer +3. **Chain descriptors**: Set each descriptor's `next` field to the address of the following descriptor. Use `0xFFFFFFFF_FFFFFFFF` to mark the end of the chain +4. **Write first descriptor address** to the `desc_addr` register. This register is part of the descriptor frontend's own small register file (separate from the descriptor memory). Writing a non-zero address to it triggers the fetch engine +5. **Hardware fetches autonomously**: The frontend reads descriptors over AXI, submits them to the backend, and follows the `next` pointer chain +6. **Wait for completion**: Poll the status register (bit 0 = busy) or wait for the IRQ (if `flags.irq` is set) + +## Speculative Prefetch + +The `NSpeculation` parameter controls how many descriptors the frontend may fetch ahead of the backend's consumption. This hides the descriptor fetch latency — while the backend processes one transfer, the frontend is already reading the next `NSpeculation` descriptors from memory. Setting `NSpeculation=0` disables prefetching (each descriptor is fetched only after the previous transfer completes). + +Set `NSpeculation` to match your expected descriptor chain length or `NumAxInFlight`, whichever is smaller. Higher values waste memory bandwidth on speculative reads if chains are short. For most systems, `NSpeculation=4` is a good default. + +## Source Files + +- `src/frontend/desc64/idma_desc64_top.sv` — Top-level module +- `src/frontend/desc64/idma_desc64_reg_wrapper.sv` — Register interface wrapper +- `src/frontend/desc64/idma_desc64_reshaper.sv` — Descriptor-to-request conversion diff --git a/doc/site/src/content/docs/architecture/frontend/index.md b/doc/site/src/content/docs/architecture/frontend/index.md new file mode 100644 index 00000000..9efdabd0 --- /dev/null +++ b/doc/site/src/content/docs/architecture/frontend/index.md @@ -0,0 +1,36 @@ +--- +title: Frontend +description: Frontends accept transfer descriptors from the platform and emit iDMA requests. +--- + +## Frontend Role + +The frontend is the topmost layer of the iDMA pipeline. It provides the software-visible interface through which the host or an accelerator core submits transfer descriptors. iDMA ships three frontend families, each targeting a different integration style: + +- **[Register Frontend](./register/)** — memory-mapped register interface (`reg64_2d`) +- **[Snitch Frontend](./snitch/)** — ISA-coupled frontend for Snitch cores (`inst64`) +- **[Descriptor Frontend](./descriptor/)** — descriptor-ring frontend (`desc64`) + +## Choosing a Frontend + +| | Register | Descriptor | Snitch | +|---|---------|-----------|--------| +| **Interface** | Memory-mapped registers (PULP `reg_interface` — a lightweight request/response protocol similar to APB, used for memory-mapped register access in PULP SoCs) | Descriptor ring in shared memory (AXI) | Custom ISA extension (accelerator bus) | +| **Typical SoC** | General-purpose (CVA6, RISC-V) | CVA6 / Linux-capable | Snitch cluster | +| **Data Width** | Any | 64-bit | Any (typically 64–512 bit) | +| **ND Support** | Yes (2D via `reg64_2d`) | No (1D only) | Yes (2D, `NumDim=2`) | +| **Key Advantage** | Simple, portable | Hardware-managed queue, low CPU overhead | Single-cycle launch, zero register overhead | +| **Error Visibility** | Status register (poll `done_id`, check response) | IRQ (if `flags.irq` set) | Poll via `DMSTAT` | + +:::note[Figure placeholder] +Diagram: frontend selection decision flow. +Show Snitch decision first, then descriptor vs register based on queue needs. +::: + +## Common Pattern + +All frontends produce `idma_req_t` (or `idma_nd_req_t` for ND-capable frontends) and consume `idma_rsp_t`. Frontends are interchangeable at the `idma_req_t` / `idma_rsp_t` boundary, but each has a different control plane: register bus, AXI (descriptor fetch), or accelerator interface. Switching frontends requires re-wiring the host-side interface. + +## Generated Variants + +The register frontend is **generated** from Mako templates (`src/frontend/reg/tpl/`) by the MARIO framework, producing variants like `idma_reg64_2d`. The descriptor (`desc64`) and Snitch (`inst64`) frontends are **hand-written** SystemVerilog in `src/frontend/desc64/` and `src/frontend/inst64/` respectively. diff --git a/doc/site/src/content/docs/architecture/frontend/register.md b/doc/site/src/content/docs/architecture/frontend/register.md new file mode 100644 index 00000000..fffc05c5 --- /dev/null +++ b/doc/site/src/content/docs/architecture/frontend/register.md @@ -0,0 +1,138 @@ +--- +title: Register Frontend +description: Memory-mapped register interface for submitting DMA transfers. +--- + +## Register Frontend Role + +The register frontend (`idma_reg64_2d`) exposes a standard memory-mapped register file through which software configures and launches DMA transfers. It connects via the PULP register interface and is the most common frontend for general-purpose SoCs. The module is generated from `src/frontend/reg/tpl/idma_reg.sv.tpl`. + +## Parameters + +| Parameter | Default | Description | +|-----------|---------|-------------| +| `NumRegs` | 1 | Number of configuration register ports (parallel access points) | +| `NumStreams` | 1 | Number of independent DMA streams (max 16). Each stream has its own transfer ID counter | +| `IdCounterWidth` | 32 | Width of the transfer ID counter (max 32-bit) | + +## Programming Sequence + +1. **Write transfer parameters**: Set `src_addr`, `dst_addr`, `num_bytes`, and optionally `reps`/`src_stride`/`dst_stride` for 2D mode +2. **Write configuration**: Set `conf` with the desired decouple flags, protocol selection, and ND mode enable. Stream selection is implicit in which `next_id[stream]` register you read in the next step +3. **Read `next_id[stream]`**: This read atomically launches the transfer on the selected stream and returns the assigned transfer ID. The register port stalls (backpressures the bus) until the backend accepts the request +4. **Poll `done_id[stream]`**: Wait until `done_id >= next_id` to confirm completion + +:::caution[Side-effect read] +Reading the `next_id` register has a side effect — it atomically launches the configured transfer. This atomic read-launch mechanism prevents race conditions in multi-core systems — the bus stall guarantees that the transfer parameters are consumed before another core can overwrite them. This is non-standard register behavior; ensure your driver reads `next_id` exactly once per transfer. +::: + +## Register Map + +The register file provides direct access to all fields of the `idma_req_t` / `idma_nd_req_t` structs. Software writes the transfer parameters, then reads `next_id` to atomically submit the request: + +:::note[32-bit register bus] +The register bus is 32 bits wide. 64-bit values (addresses, lengths, strides) are split across `_low` and `_high` register pairs (e.g., `src_addr_low` at offset 0xDC, `src_addr_high` at offset 0xE0). The simplified names in the table below refer to the logical fields; see the generated register description (`target/rtl/idma_reg64_2d.hjson`) for exact offsets and bit layouts. +::: + +**Transfer Parameters** — set these before launching a transfer: + +| Register | Access | Description | +|----------|--------|-------------| +| `src_addr` | R/W | Source address for the next transfer | +| `dst_addr` | R/W | Destination address for the next transfer | +| `num_bytes` | R/W | Transfer length in bytes | + +**Configuration** — controls decoupling, burst limits, protocol selection, and ND mode: + +| Register | Access | Description | +|----------|--------|-------------| +| `conf` | R/W | Transfer configuration (see below) | + +**Control/Status** — `next_id` launches the transfer; `done_id` signals completion: + +| Register | Access | Description | +|----------|--------|-------------| +| `status` | RO | Per-stream busy flags | +| `next_id` | RO | Per-stream next transfer ID. **Reading launches the transfer** | +| `done_id` | RO | Per-stream last completed transfer ID | + +**ND Mode** — only used when `enable_nd` is set in `conf`: + +| Register | Access | Description | +|----------|--------|-------------| +| `reps` | R/W | Number of 2D repetitions (ND mode) | +| `src_stride` | R/W | Source stride between rows (ND mode) | +| `dst_stride` | R/W | Destination stride between rows (ND mode) | + +### Configuration Register (`conf`) + +| Bits | Field | Description | +|------|-------|-------------| +| 0 | `decouple_aw` | Enable R-AW coupling (hold write addresses until read data arrives) | +| 1 | `decouple_rw` | Fully decouple read and write channels | +| 2 | `src_reduce_len` | Shorten source bursts beyond page-boundary splitting | +| 3 | `dst_reduce_len` | Shorten destination bursts | +| 6:4 | `src_max_llen` | Max source burst length as log2(beats) | +| 9:7 | `dst_max_llen` | Max destination burst length as log2(beats) | +| 10 | `enable_nd` | Enable ND mode (use previously set `reps`/`src_stride`/`dst_stride`) | +| 13:11 | `src_protocol` | Source protocol select (`protocol_e` enum) | +| 16:14 | `dst_protocol` | Destination protocol select (`protocol_e` enum) | + +## Multi-Port Arbitration + +When `NumRegs > 1`, multiple register ports can submit transfers concurrently. An internal round-robin arbiter serializes requests to the single backend interface. Each port stalls independently on its `next_id` read until its request is accepted. This allows multiple cores to share a single DMA without software-level locking. + +:::note[Figure placeholder] +Diagram: register frontend sequence. +Show write parameters, read `next_id` launching the transfer, and polling `done_id` until completion. +::: + +## Worked Example: 1 KiB Transfer + +The following register writes launch a 1 KiB AXI-to-AXI transfer from `0x8000_0000` to `0xC000_0000` with R-AW coupling enabled, on stream 0: + +``` +// 1. Write transfer parameters +write(src_addr_low, 0x80000000); +write(src_addr_high, 0x00000000); +write(dst_addr_low, 0xC0000000); +write(dst_addr_high, 0x00000000); +write(num_bytes_low, 1024); +write(num_bytes_high, 0); + +// 2. Write configuration: decouple_aw=1, everything else default (AXI=0) +write(conf, 0x1); // bit 0 = decouple_aw + +// 3. Read next_id[0] — launches the transfer, returns transfer ID +tid = read(next_id_0); + +// 4. Poll for completion +while (read(done_id_0) < tid); +``` + +## Worked Example: 2D Transfer + +The following register writes launch a 2D transfer copying 4 rows of 64 bytes with different source and destination strides: + +``` +// 2D example: copy 4 rows of 64 bytes, src stride 256, dst stride 64 +write(num_bytes_low, 64); +write(num_bytes_high, 0); +write(src_addr_low, 0x80000000); +write(src_addr_high, 0x00000000); +write(dst_addr_low, 0xC0000000); +write(dst_addr_high, 0x00000000); +write(reps, 4); +write(src_stride_low, 256); +write(src_stride_high, 0); +write(dst_stride_low, 64); +write(dst_stride_high, 0); +write(conf, 0x401); // bit 0 = decouple_aw, bit 10 = enable_nd +tid = read(next_id_0); +while (read(done_id_0) < tid); +``` + +## Source Files + +- **Template**: `src/frontend/reg/tpl/idma_reg.sv.tpl` +- **Generated output**: `target/rtl/idma_reg64_2d.sv`, `target/rtl/idma_reg32_2d.sv` diff --git a/doc/site/src/content/docs/architecture/frontend/snitch.md b/doc/site/src/content/docs/architecture/frontend/snitch.md new file mode 100644 index 00000000..09090194 --- /dev/null +++ b/doc/site/src/content/docs/architecture/frontend/snitch.md @@ -0,0 +1,95 @@ +--- +title: Snitch Frontend +description: ISA-coupled frontend for Snitch cores using Xdma custom instructions. +--- + +## Snitch Frontend Role + +The Snitch frontend (`idma_inst64_top`) is tightly coupled to the Snitch RISC-V core through custom Xdma ISA extensions. DMA transfers are launched directly from the instruction stream via the accelerator bus interface, eliminating register file overhead and enabling single-cycle transfer submission. + +![Snitch Integration](/fig/system_integration_alt.svg) + +## Xdma Instruction Set + +A DMA transfer requires three steps: (1) set the source and destination addresses (`DMSRC`, `DMDST`), (2) launch the transfer with a length and config (`DMCPY`/`DMCPYI`), (3) poll for completion (`DMSTAT`/`DMSTATI`). Optional instructions set 2D parameters (`DMSTR`, `DMREP`) and AXI user fields (`DMUSER`). + +All DMA instructions that return a value write to `rd` (destination register). The assembly syntax is `DMCPYI rd, rs1, imm` — `rd` receives the transfer ID, `rs1` provides the length. + +| Instruction | Operands | Description | +|-------------|----------|-------------| +| `DMSRC` | `rs1` (low 32b), `rs2` (high bits) | Set source address | +| `DMDST` | `rs1` (low 32b), `rs2` (high bits) | Set destination address | +| `DMCPYI` | `rd` = transfer ID, `rs1` = length, imm = {channel, config} | Launch transfer (immediate config). Returns transfer ID in `rd` | +| `DMCPY` | `rd` = transfer ID, `rs1` = length, `rs2` = {channel, config} | Launch transfer (register config). Returns transfer ID in `rd` | +| `DMSTATI` | `rd` = status value, imm = {channel, status_sel} | Query status (immediate). Returns status in `rd` | +| `DMSTAT` | `rd` = status value, `rs2` = {channel, status_sel} | Query status (register). Returns status in `rd` | +| `DMSTR` | `rs1` = src_stride, `rs2` = dst_stride | Set 2D strides | +| `DMREP` | `rs1` = repetitions | Set 2D repetition count | +| `DMUSER` | `rs1`, `rs2` | Set AXI user field. When `AxiUserWidth <= 32`, only `rs1` is used (lower bits). When `AxiUserWidth > 32`, `rs1` provides bits [31:0] and `rs2` provides the remaining upper bits | + +**Status select values** (`DMSTAT`/`DMSTATI`): +- `0`: Completed transfer ID — compare against the ID returned by `DMCPY` to check if a specific transfer has finished +- `1`: Next transfer ID — the ID that will be assigned to the next submitted transfer +- `2`: Busy flag — 1 if any transfer is in-flight on this channel +- `3`: Backend FIFO full flag — 1 if the request FIFO is full; software should wait before submitting more transfers + +**Config field** (`DMCPY`/`DMCPYI`): +- Bit 0: Reserved +- Bit 1: Enable 2D mode (use previously set strides/reps). If 2D mode is enabled but `DMSTR`/`DMREP` were not called since the last transfer, the previously set stride and repetition values are reused. On reset, these default to zero +- Bits 4:2: Channel select — `$clog2(NumChannels)` bits wide, remaining upper bits are zero-extended. For the common single-channel case (`NumChannels=1`), these bits are unused and only bit 1 (2D enable) matters + +## Parameters + +For most Snitch cluster integrations, `NumChannels=1` and `NumAxInFlight=3` are standard. Increase `NumChannels` only if you need independent DMA channels on separate address spaces. + +| Parameter | Description | +|-----------|-------------| +| `AxiDataWidth` | AXI data bus width | +| `AxiAddrWidth` | AXI address width | +| `AxiUserWidth` | AXI user signal width (max 64 bits) | +| `AxiIdWidth` | AXI ID width | +| `NumAxInFlight` | Number of in-flight AXI transactions (default: 3) | +| `DMAReqFifoDepth` | Depth of the request FIFO between frontend and midend (default: 3) | +| `NumChannels` | Number of independent DMA channels, each with its own backend + ND midend (default: 1) | +| `DMATracing` | Enable DMA trace file generation for debugging | + +## Programming Sequence + +The following assembly sequence demonstrates a complete 2D DMA transfer with polling completion: + +```asm +# 1. Set source address +DMSRC a0, a1 # src_addr = {a1, a0} + +# 2. Set destination address +DMDST a2, a3 # dst_addr = {a3, a2} + +# 3. (Optional) Set 2D parameters +DMSTR a4, a5 # src_stride = a4, dst_stride = a5 +DMREP a6 # reps = a6 + +# 4. Launch transfer (2D mode on channel 0) +DMCPYI t0, a7, 0b010 # t0 = transfer_id, config[1]=1 (2D mode) + +# 5. Poll for completion +loop: + DMSTATI t1, 0b000 # t1 = completed_id on channel 0 + blt t1, t0, loop # Wait until completed_id >= transfer_id +``` + +:::note[Figure placeholder] +Diagram: Snitch instruction flow. +Show DMSRC/DMDST setup, DMSTR/DMREP for ND, DMCPY launch, DMSTAT polling. +::: + +## Internal Architecture + +The `idma_inst64_top` module instantiates `NumChannels` independent backends, each paired with an ND midend (`NumDim=2`, `BufferDepth=3`). The frontend instruction decoder fills an `idma_nd_req_t` struct from the instruction stream and routes it to the selected channel's request FIFO. A per-channel transfer ID generator tracks issue and retire events. Each backend produces separate AXI read and write manager ports. The `axi_rw_join` module merges them into a single AXI manager port for connection to the SoC interconnect. + +When `NumChannels > 1`, each channel has its own independent backend and ND midend. The channel is selected via the config field in `DMCPY`/`DMCPYI` (bits 4:2). Channels operate independently — one can be busy while another accepts new transfers. The AXI ports from all channels are merged via `axi_rw_join`, so they share bus bandwidth. + +## Source Files + +- `src/frontend/inst64/idma_inst64_top.sv` — Top-level module +- `src/frontend/inst64/idma_inst64_snitch_pkg.sv` — Instruction encodings +- `src/frontend/inst64/idma_inst64_events.sv` — Performance event counters diff --git a/doc/site/src/content/docs/architecture/interfaces.md b/doc/site/src/content/docs/architecture/interfaces.md new file mode 100644 index 00000000..a729d833 --- /dev/null +++ b/doc/site/src/content/docs/architecture/interfaces.md @@ -0,0 +1,74 @@ +--- +title: Interfaces and Types +description: Request, response, and option structs used across iDMA layers. +--- + +## Interface Reference + +This page is the reference for `idma_req_t`, `options_t`, and `idma_rsp_t`. Use it when writing drivers or connecting custom frontends. For integration, prefer the convenience macros from `typedef.svh`. + +## Transfer Request (`idma_req_t`) + +The request carries addresses, transfer length, and options that control protocol and backend behavior. + +```verilog +`IDMA_TYPEDEF_REQ_T(idma_req_t, tf_len_t, axi_addr_t, options_t) +// Expands to: +typedef struct packed { + tf_len_t length; // Transfer length in bytes + axi_addr_t src_addr; // Source byte address + axi_addr_t dst_addr; // Destination byte address + user_t user; // User-defined sideband data + options_t opt; // Transfer options +} idma_req_t; +``` + +## Transfer Options (`options_t`) + +Transfer options select protocols and carry sideband signals. Each request embeds one `options_t`. + +```verilog +`IDMA_TYPEDEF_OPTIONS_T(options_t, axi_id_t) +// Expands to: +typedef struct packed { + idma_pkg::protocol_e src_protocol; // Source bus protocol + idma_pkg::protocol_e dst_protocol; // Destination bus protocol + axi_id_t axi_id; // AXI transaction ID + idma_pkg::axi_options_t src; // Source AXI options + idma_pkg::axi_options_t dst; // Destination AXI options + idma_pkg::backend_options_t beo; // Backend engine options + logic last; // Last transfer flag (for midend) +} options_t; +``` + +## Transfer Response (`idma_rsp_t`) + +The response indicates completion and error status for a transfer. + +```verilog +`IDMA_TYPEDEF_RSP_T(idma_rsp_t, err_payload_t) +// Expands to: +typedef struct packed { + logic last; // Last response for this ND transfer + logic error; // Error occurred + err_payload_t pld; // Error details (cause, type, address) +} idma_rsp_t; +``` + +## Error Payload (`err_payload_t`) + +The error payload identifies the faulting burst and its origin. + +```verilog +`IDMA_TYPEDEF_ERR_PAYLOAD_T(err_payload_t, axi_addr_t) +// Expands to: +typedef struct packed { + axi_pkg::resp_t cause; // AXI response code + idma_pkg::err_type_t err_type; // Error source (BUS_READ, BUS_WRITE, BACKEND, ND_MIDEND) + axi_addr_t burst_addr; // Address of the faulting burst +} err_payload_t; +``` + +## Handshake Semantics + +All request and response interfaces use ready/valid handshaking. A transfer is accepted when `req_valid_i` and `req_ready_o` are both high in the same cycle. A response is accepted when `rsp_valid_o` and `rsp_ready_i` are both high. diff --git a/doc/site/src/content/docs/architecture/midend.md b/doc/site/src/content/docs/architecture/midend.md new file mode 100644 index 00000000..3e98aa56 --- /dev/null +++ b/doc/site/src/content/docs/architecture/midend.md @@ -0,0 +1,149 @@ +--- +title: Midend +description: The midend decomposes multi-dimensional and round-trip transfers into 1D requests. +--- + +## Midend Role + +The midend sits between the frontend and backend. It accepts N-dimensional or round-trip transfer descriptors and decomposes them into a stream of 1D requests that the backend can execute. The midend is **optional** — for systems that only need 1D transfers, the frontend can drive the backend directly. **Use the ND midend** when your transfers are 2D or higher (e.g., tiling a matrix, copying framebuffer rows with stride). **Skip the midend** (connect frontend directly to backend) when all your transfers are 1D contiguous copies — the midend adds latency and area for no benefit in this case. See the [System Integration](../guides/system-integration/) guide for wiring examples showing how the midend connects to the frontend and backend. + +Four midend variants are available: + +| Variant | Module | Purpose | +|---------|--------|---------| +| **ND** | `idma_nd_midend` | Multi-dimensional transfer decomposition | +| **RT** | `idma_rt_midend` | Event-driven periodic (round-trip) transfers | +| **MP_DIST** | `idma_mp_dist_midend` | Distribute transfers across multiple backends by address | +| **MP_SPLIT** | `idma_mp_split_midend` | Split transfers at region boundaries for a single backend | + +## ND Midend + +The ND midend (`idma_nd_midend`) decomposes an N-dimensional transfer into a sequence of 1D transfers. After each 1D burst completes, the midend checks whether the current dimension has remaining repetitions. If so, it adds the dimension's stride to the address and emits the next burst. When a dimension exhausts its repetitions, the next-higher dimension increments. Internally, this is implemented with cascaded counters (one per dimension) and a popcount-based selector that handles simultaneous dimension overflows. + +### ND Parameters + +| Parameter | Description | +|-----------|-------------| +| `NumDim` | Number of dimensions. Must be >= 2 (dimension 1 is the 1D burst handled by the backend) | +| `RepWidths` | Per-dimension counter widths — an array specifying the counter width for each dimension. For example, with `NumDim=3` and `RepWidths = '{32, 16, 8}`, dimension 1 supports up to 2³² repetitions, dimension 2 up to 2¹⁶, etc. | + +### Request Types + +The ND request wraps a 1D `idma_req_t` with per-dimension stride/repetition descriptors: + +```verilog +`IDMA_TYPEDEF_D_REQ_T(idma_d_req_t, reps_t, strides_t) +// Expands to: +typedef struct packed { + reps_t reps; // Number of repetitions for this dimension + strides_t src_strides; // Source address stride (bytes) + strides_t dst_strides; // Destination address stride (bytes) +} idma_d_req_t; + +`IDMA_TYPEDEF_ND_REQ_T(idma_nd_req_t, idma_req_t, idma_d_req_t) +// Expands to: +typedef struct packed { + idma_req_t burst_req; // Base 1D request + idma_d_req_t [NumDim-2:0] d_req; // Per-dimension descriptors +} idma_nd_req_t; +``` + +### Worked Example: 2D Transfer + +Consider a 2D transfer copying a 64-byte row repeated 4 times with different source and destination pitches. For this transfer, the request parameters are: + +``` +NumDim = 2 +length = 64 (bytes per row) +reps = 4 (number of rows) +src_stride = 128 (source row pitch) +dst_stride = 64 (destination row pitch, tightly packed) +``` + +The ND midend emits 4 sequential 1D transfers: + +| Iteration | src_addr | dst_addr | length | +|-----------|----------|----------|--------| +| 0 | `base_src + 0` | `base_dst + 0` | 64 | +| 1 | `base_src + 128` | `base_dst + 64` | 64 | +| 2 | `base_src + 256` | `base_dst + 128` | 64 | +| 3 | `base_src + 384` | `base_dst + 192` | 64 | + +:::note[Figure placeholder] +Diagram: 2D transfer memory layout. +Show source rows with stride gaps and destination rows packed tightly. +::: + +:::note[Zero repetitions] +If all repetition counts for a dimension are zero, that dimension is treated as a no-op ("zero stage"). The midend signals this as an `ND_MIDEND` error in the response. +::: + +## RT Midend + +The RT midend (`idma_rt_midend`) supports event-driven periodic transfers. It is designed for periodic data movement — sensor sampling at fixed intervals, display buffer refresh, or ring-buffer rotation. Each event channel triggers its pre-configured transfer when its countdown reaches zero, without CPU intervention. + +It contains `NumEvents` countdown counters, each triggering an ND transfer when its counter reaches zero. A round-robin arbiter selects among ready events, and a bypass path allows non-periodic transfers to pass through. + +**Example**: A sensor sampling system needs to copy 256 bytes from sensor MMIO (`0x4000_0000`) to a ring buffer (`0x8000_0000`) every 1000 clock cycles. Configure event channel 0 with: `src_addr = 0x4000_0000`, `dst_addr = 0x8000_0000`, `length = 256`, `countdown = 1000`. The RT midend will autonomously re-trigger this transfer every 1000 cycles. + +### RT Parameters + +| Parameter | Description | +|-----------|-------------| +| `NumEvents` | Number of parallel event channels | +| `EventCntWidth` | Width of the countdown counters (period in clock cycles) | +| `NumOutstanding` | Maximum outstanding transfers (depth of the response routing FIFO) | + +### Operation + +1. Software configures each event channel with: source/destination addresses, transfer length, 2D strides/repetitions, and a countdown threshold. Configuration is submitted through the module's `nd_req_i` port — software sends ND requests with an event channel ID. The countdown threshold and enable signals are separate input ports +2. Each enabled counter decrements every clock cycle +3. On overflow (reaching zero), the counter's pre-configured ND request is submitted to the arbiter +4. A round-robin arbiter (`stream_arbiter`) selects among triggered events +5. The bypass path allows direct ND requests to be interleaved with periodic ones via a second round-robin arbiter +6. A response FIFO routes completions back to the correct requester (periodic or bypass) + +## Multicore Midends + +:::note[Figure placeholder] +Diagram: MP_DIST vs MP_SPLIT. +Show parallel distribution across multiple backends vs serialized region splits to a single backend. +::: + +### MP_DIST + +Use MP_DIST when your SoC has multiple memory banks and you want a single transfer to be distributed across backends, each serving a contiguous address region (e.g., tightly-coupled data memory in a cluster). + +The distributed midend (`idma_mp_dist_midend`) splits a single transfer across `NumBEs` backends based on address regions. Each backend owns a contiguous `RegionWidth`-byte slice within the range `[RegionStart, RegionEnd)`. The following parameters control the address region mapping: + +| Parameter | Description | +|-----------|-------------| +| `NumBEs` | Number of backends to distribute across | +| `RegionWidth` | Size of each backend's address region in bytes | +| `RegionStart` | Base address of the distributed region | +| `RegionEnd` | End address of the distributed region | +| `AddrWidth` | Address width | +| `PrintInfo` | Print debug info on transfers | + +The midend uses a `stream_fork` to fan out the request to all backends simultaneously. Backends whose region does not overlap the transfer receive a suppressed request (valid deasserted, ready tied high). Completion is signaled only when all involved backends have finished. + +### MP_SPLIT + +Use MP_SPLIT when a single transfer may span multiple address regions that require separate handling (e.g., crossing from one memory bank to another), and you want the hardware to serialize the sub-transfers automatically. + +The split midend (`idma_mp_split_midend`) serializes a transfer that spans multiple `RegionWidth` boundaries into a sequence of region-aligned sub-transfers for a single backend. It uses a two-state FSM (`Idle` / `Busy`) to emit the first region-clipped transfer immediately, then iterates through remaining regions. The following parameters define the region layout: + +| Parameter | Description | +|-----------|-------------| +| `RegionWidth` | Size of each region in bytes | +| `RegionStart` | Base address of the managed region | +| `RegionEnd` | End address of the managed region | +| `AddrWidth` | Address width | +| `PrintInfo` | Print debug info on transfers | + +## Source Files + +- `src/midend/idma_nd_midend.sv` — ND midend + counter submodule +- `src/midend/idma_rt_midend.sv` — RT midend +- `src/midend/idma_mp_dist_midend.sv` — Distributed multicore midend +- `src/midend/idma_mp_split_midend.sv` — Split multicore midend diff --git a/doc/site/src/content/docs/architecture/programming-model.md b/doc/site/src/content/docs/architecture/programming-model.md new file mode 100644 index 00000000..f3b6e9b7 --- /dev/null +++ b/doc/site/src/content/docs/architecture/programming-model.md @@ -0,0 +1,32 @@ +--- +title: Programming Model +description: How requests flow through frontend, midend, and backend. +--- + +## Model Overview + +iDMA’s programming model centers on a request/response contract. Frontends emit `idma_req_t` (or `idma_nd_req_t`), the backend executes the transfer, and the response `idma_rsp_t` signals completion or error. + +:::note[Figure placeholder] +Diagram: request lifecycle showing frontend submit, optional ND decomposition, backend legalizer/transport, and response path back to software. +::: + +## 1D Transfers + +A 1D transfer copies a contiguous byte range from `src_addr` to `dst_addr`. It is the native backend format. If you submit 1D requests, you can bypass the midend entirely. + +## ND Transfers + +ND transfers (2D/3D) are decomposed into a series of 1D transfers by the midend. Each dimension defines a repetition count and stride. The midend emits a stream of 1D bursts while preserving ordering and optional error semantics. + +## Request Lifecycle + +1. Frontend validates inputs and forms a request. +2. Midend (optional) expands ND into 1D. +3. Backend legalizer splits into protocol-legal bursts. +4. Transport layer executes bus reads/writes and realigns data. +5. Response is emitted when all bursts complete. + +## Error Handling Choices + +Error handling is a policy decision. The backend can be configured to continue on error, abort a transfer, or replay. Frontends interpret responses and decide how to recover. See [Error Handling](../../guides/error-handling/) for policies and software handling patterns. diff --git a/doc/site/src/content/docs/guides/docs-verification.md b/doc/site/src/content/docs/guides/docs-verification.md new file mode 100644 index 00000000..4edac0b3 --- /dev/null +++ b/doc/site/src/content/docs/guides/docs-verification.md @@ -0,0 +1,40 @@ +--- +title: Docs Verification Plan +description: Quality checks to ensure iDMA docs are accurate, complete, and usable. +--- + +## Docs QA Overview + +This plan defines how we verify documentation quality. It complements the RTL verification guide and focuses on correctness, clarity, and navigability of the docs. + +## Build Checks + +Run the docs build and fail on warnings: + +```bash +cd doc/site +npm run build +``` + +## Consistency Checklist + +- All parameter tables include descriptions. +- All interface fields are defined and explained. +- No unresolved TODOs or “TBD” remain without a clear status. +- All links and image references resolve. + +## Snippet Rule + +Every code block must be preceded by a paragraph explaining the intent, context, and expected outcome. This prevents code dumps without guidance. + +## Diagram Coverage + +Each major section should include a diagram or a visible placeholder box describing the intended figure and its educational purpose. + +## Accuracy Review + +Review key claims against the top-level interface definitions and integration examples. Avoid copying RTL structure into documentation; describe behavior and constraints instead. + +## Final Readability Pass + +Check for terminology consistency and avoid ambiguities in terms like “decouple,” “couple,” and “legalize.” diff --git a/doc/site/src/content/docs/guides/error-handling.md b/doc/site/src/content/docs/guides/error-handling.md new file mode 100644 index 00000000..fbdd8074 --- /dev/null +++ b/doc/site/src/content/docs/guides/error-handling.md @@ -0,0 +1,110 @@ +--- +title: Error Handling +description: How iDMA reports and propagates errors across the frontend, midend, and backend. +--- + +## Error Handling Overview + +iDMA propagates error information from the backend (bus-level faults) back through the midend to the frontend, where software can read error status registers. Error handling is optional — controlled by the `ErrorCap` parameter. When enabled (`ErrorCap = ERROR_HANDLING`), the error handler FSM monitors datapath responses and gives software the choice to continue or abort a faulting transfer. + +## Error Types + +From `err_type_e` in `idma_pkg.sv`: + +| Value | Name | Description | +|-------|------|-------------| +| `2'b00` | `BUS_READ` | AXI read channel returned a non-OKAY response | +| `2'b01` | `BUS_WRITE` | AXI write channel returned a non-OKAY response | +| `2'b10` | `BACKEND` | Internal backend error (currently: transfer length == 0) | +| `2'b11` | `ND_MIDEND` | ND midend error (all repetition counts are zero) | + +## Error Response + +Every transfer produces an `idma_rsp_t` response. If `error == 0`, the transfer succeeded and `pld` is undefined (ignore it). If `error == 1`, the payload contains the error details: + +```verilog +typedef struct packed { + axi_pkg::resp_t cause; // AXI response code (SLVERR, DECERR) + idma_pkg::err_type_t err_type; // BUS_READ, BUS_WRITE, BACKEND, or ND_MIDEND + axi_addr_t burst_addr; // Address of the faulting burst +} err_payload_t; + +typedef struct packed { + logic last; // Last response in this transfer sequence + logic error; // 1 = error occurred + err_payload_t pld; // Error details +} idma_rsp_t; +``` + +The `burst_addr` field reports the base address of the AXI burst that faulted — this is the address from the AR or AW channel, not the individual beat address. + +## Error Handler FSM + +:::note[Figure placeholder] +Diagram: error handler FSM states and transitions. +Show IDLE, WAIT, WAIT_LAST_W, EMIT_EXTRA_RSP, LEG_FLUSH and the CONTINUE/ABORT paths. +::: + +The error handler (`idma_error_handler`) implements a 5-state FSM: + +| State | Description | Transition | +|-------|-------------|------------| +| `IDLE` | Pass-through mode. Monitors R and W datapath responses for non-OKAY | -> `WAIT` on read error; -> `WAIT` or `WAIT_LAST_W` on write error | +| `WAIT` | Error reported to software. Waiting for CONTINUE or ABORT action | -> `IDLE` on CONTINUE; -> `IDLE` if ABORT with multiple outstanding; -> `LEG_FLUSH` if ABORT with single outstanding | +| `WAIT_LAST_W` | Like WAIT, but the error occurred on the last write burst of a 1D transfer. Requires an extra response after handling | -> `EMIT_EXTRA_RSP` on CONTINUE; -> `EMIT_EXTRA_RSP` if ABORT with multiple outstanding; -> `LEG_FLUSH` if ABORT with single outstanding | +| `EMIT_EXTRA_RSP` | Send the completion response that was deferred due to the error | -> `IDLE` when response is accepted | +| `LEG_FLUSH` | Flush the legalizer: drain remaining bursts, poison data (drive all-zero strobes on remaining write bursts so the destination memory is not corrupted by stale buffer contents), then kill the active transfer | -> `EMIT_EXTRA_RSP` when datapath is idle | + +The `WAIT_LAST_W` state exists because write errors on the last burst of a transfer require special handling. Normally, the backend emits a completion response when the last write finishes. But if that last write *also* faults, the error response must be sent *before* the completion response, requiring an extra `EMIT_EXTRA_RSP` state. + +Read errors have higher priority than write errors — if both occur simultaneously, the read error is reported first. + +## Actions + +Software responds to an error via the `idma_eh_req_t` interface: + +| Action | Value | Behavior | +|--------|-------|----------| +| `CONTINUE` | `1'b0` | Complete the remaining bursts of the current 1D transfer normally. Data for the faulting burst is undefined | +| `ABORT` | `1'b1` | Abort the current 1D transfer. The legalizer is flushed (remaining bursts suppressed) and the datapath drains. If multiple 1D transfers are outstanding, abort degrades to continue (see below) | + +**Data integrity on CONTINUE**: When a read error occurs, the data for that burst is undefined (whatever the bus returned). The buffer may contain partial or garbage data. If CONTINUE is selected, subsequent bursts are read normally but the faulting burst's data is corrupted in the destination. + +**ABORT degradation**: When multiple 1D transfers are queued in the legalizer, aborting would require flushing transfers that may have already issued bus requests. Since AXI requires all issued bursts to complete, flushing mid-stream would leave the bus in an inconsistent state. Therefore, ABORT only takes effect when a single transfer is outstanding; otherwise it degrades to CONTINUE. + +### Worked Example + +The DMA reads 256 bytes starting at `0x1000`. At address `0x1040`, the slave returns SLVERR. The error handler reports: `err_type = BUS_READ`, `cause = SLVERR`, `burst_addr = 0x1000` (the burst base, not `0x1040`). Software issues CONTINUE. The remaining bursts complete normally, but the 64-byte burst containing `0x1040` has undefined data at the destination. + +## Software Handling Pattern + +1. **Launch transfer**: Submit `idma_req_t` through the frontend +2. **Wait for response**: Poll or wait for `rsp_valid` +3. **Check `rsp.error`**: If 0, transfer completed successfully +4. **Read error details**: Extract `rsp.pld.err_type`, `rsp.pld.cause`, and `rsp.pld.burst_addr` +5. **Issue action**: Write CONTINUE or ABORT to the error handler request interface (`idma_eh_req_i` + `eh_req_valid_i`), then wait for the final completion response. Note: this is a raw backend port. How it is exposed depends on the frontend: in register-based systems, the SoC typically connects it to a dedicated control register. In Snitch systems, the response is returned through `DMSTAT` polling. The descriptor frontend does not expose an error handler action interface — errors are reported via IRQ only + +## Error Visibility by Frontend + +How errors reach software depends on the frontend: + +- **Register frontend**: Poll `done_id` until it advances. The corresponding `idma_rsp_t` is emitted on the backend's response port. If `rsp.error == 1`, the error payload fields indicate the cause. The SoC wrapper must route the response to a readable status register +- **Descriptor frontend**: Signals errors via IRQ (if `flags.irq` is set in the descriptor) +- **Snitch frontend**: Returns error information through `DMSTAT` polling + +## After Error Recovery + +After issuing CONTINUE or ABORT and receiving the final completion response, the backend returns to normal operation. No reset is required. You can submit new transfers immediately. However, if the error was caused by a hardware fault (e.g., disconnected slave), subsequent transfers to the same address range will also fail. + +## Constraints + +- **AXI-to-AXI only**: The error handler is only instantiated for backend variants with a single AXI read port and a single AXI write port (i.e., the `rw_axi` variant). Mixed-protocol variants (`r_obi_w_axi`, `r_axi_w_obi`) and multi-port variants (`rw_axi_rw_axis`) will produce a fatal elaboration error (`$fatal`) if `ErrorCap = ERROR_HANDLING`. See the [Backend](../architecture/backend/) page for the full variant matrix +- **ErrorCap parameter**: Must be set at elaboration time. When `NO_ERROR_HANDLING`, all error signals are tied to neutral values and the error handler is bypassed +- **AXI compliance**: Once a burst is issued, all beats must complete — the error handler cannot cancel individual beats mid-burst. ABORT takes effect at burst boundaries +- **Outstanding transfer limit**: The error handler tracks outstanding transfers with a credit counter sized to `MetaFifoDepth`. The `cnt_busy` signal indicates transfers are still in-flight + +## Source Files + +- `src/backend/idma_error_handler.sv` — Error handler FSM +- `src/idma_pkg.sv` — Error type definitions (`err_type_e`, `eh_action_e`, `error_cap_e`) +- `src/include/idma/typedef.svh` — `err_payload_t` macro diff --git a/doc/site/src/content/docs/guides/performance-limitations.md b/doc/site/src/content/docs/guides/performance-limitations.md new file mode 100644 index 00000000..9facb925 --- /dev/null +++ b/doc/site/src/content/docs/guides/performance-limitations.md @@ -0,0 +1,31 @@ +--- +title: Performance and Limitations +description: Constraints, tradeoffs, and tuning guidance. +--- + +## Constraints Overview + +This guide summarizes practical constraints and tradeoffs that impact performance, area, and correctness. + +## Alignment and Burst Limits + +- AXI bursts cannot cross 4 KiB boundaries. +- TileLink bursts are power-of-2 and limited by TLToAXI4 behavior. +- OBI and INIT are single-beat protocols. + +## Buffer Depth + +`BufferDepth` impacts throughput and alignment tolerance. Depth 3 is the default recommendation for mixed alignment cases; smaller depths can stall when read and write offsets differ. + +## Decoupling Tradeoffs + +- `decouple_rw=1` maximizes throughput but can deadlock if the buffer is too shallow. +- `decouple_aw=1` enables R-AW coupling, which can reduce bus contention but adds latency. + +## Outstanding Transactions + +`NumAxInFlight` controls how many bursts can be in flight. Increasing it improves throughput on high-latency buses but increases area and verification complexity. + +## Software Legalization + +If `HardwareLegalizer=0`, software must split transfers into protocol-legal bursts. This reduces hardware but shifts correctness burden to software. diff --git a/doc/site/src/content/docs/guides/quickstart.md b/doc/site/src/content/docs/guides/quickstart.md new file mode 100644 index 00000000..53a460a3 --- /dev/null +++ b/doc/site/src/content/docs/guides/quickstart.md @@ -0,0 +1,66 @@ +--- +title: Quickstart +description: Minimal steps to integrate iDMA and run a transfer. +--- + +## Quickstart Overview + +This guide shows the shortest path to an end-to-end iDMA transfer: choose a backend, define types, wire modules, and launch a request. It assumes a single clock domain and a 1D transfer flow. + +## 1. Choose a Backend Variant + +Pick the backend variant that matches your read/write protocols. For AXI-to-AXI systems, start with `rw_axi`. + +## 2. Define Types + +Use the `typedef.svh` macros to define the request/response structs you will wire between layers. + +```verilog +`include "idma/typedef.svh" + +typedef logic [AddrWidth-1:0] addr_t; +typedef logic [DataWidth-1:0] data_t; +typedef logic [IdWidth-1:0] id_t; +typedef logic [TFLenWidth-1:0] tf_len_t; + +`IDMA_TYPEDEF_FULL_REQ_T(idma_req_t, id_t, addr_t, tf_len_t) +`IDMA_TYPEDEF_FULL_RSP_T(idma_rsp_t, addr_t) +``` + +## 3. Instantiate the Backend + +Instantiate the backend and connect the request/response handshake. The exact bus ports depend on the backend variant. + +```verilog +idma_backend_rw_axi #( + .DataWidth ( DataWidth ), + .AddrWidth ( AddrWidth ), + .idma_req_t ( idma_req_t ), + .idma_rsp_t ( idma_rsp_t ), + .axi_req_t ( axi_req_t ), + .axi_rsp_t ( axi_rsp_t ) +) i_backend ( + .clk_i, + .rst_ni, + .idma_req_i ( dma_req ), + .req_valid_i ( req_valid ), + .req_ready_o ( req_ready ), + .idma_rsp_o ( dma_rsp ), + .rsp_valid_o ( rsp_valid ), + .rsp_ready_i ( rsp_ready ) + // ... bus ports ... +); +``` + +## 4. Submit a Transfer + +A frontend produces `idma_req_t`. If you do not use a frontend, you can drive the request directly from a testbench or a custom control block. + +## 5. Observe Completion + +The backend produces one `idma_rsp_t` per completed transfer. Check `error` and `err_payload_t` to determine whether the transfer succeeded. + +## Next Steps + +- For a full integration recipe, see [System Integration](../system-integration/). +- For ND transfers, see [Programming Model](../../architecture/programming-model/). diff --git a/doc/site/src/content/docs/guides/system-integration.md b/doc/site/src/content/docs/guides/system-integration.md new file mode 100644 index 00000000..7c7b8898 --- /dev/null +++ b/doc/site/src/content/docs/guides/system-integration.md @@ -0,0 +1,211 @@ +--- +title: System Integration +description: How to wire iDMA into an SoC, including type macros, parameters, and real-world examples. +--- + +## Integration Overview + +This guide covers the practical steps for integrating iDMA into a system-on-chip: choosing a frontend/midend/backend combination, instantiating the type macros, wiring the bus interfaces, and setting the key parameters. + +![System Integration](/fig/system_integration.svg) + +![System Integration (alternate view)](/fig/system_integration_alt.svg) + +## Integration Steps + +### 1. Choose Your Stack + +Select a frontend, midend, and backend based on your requirements: + +- **Backend**: Pick the variant matching your bus protocols — see the [variant matrix](../architecture/backend/#variant-matrix). If your SoC uses AXI4 throughout, `rw_axi` is the standard choice. Use `r_obi_w_axi` when reading from OBI-attached memory but writing via AXI. The Occamy variants (`r_obi_rw_init_w_axi`, `r_axi_rw_init_rw_obi`) add the INIT protocol for efficient memory zeroing. The backend page also covers [legalizer splitting rules](../architecture/backend/#splitting-rules) and [error handling](../architecture/backend/#error-handler) constraints. +- **Frontend**: Choose based on your SoC's control interface — see the [frontend comparison](../architecture/frontend/#choosing-a-frontend) +- **Midend**: Use the [ND midend](../architecture/midend/#nd-midend) for 2D/3D transfers, [RT midend](../architecture/midend/#rt-midend) for periodic transfers, or skip the midend entirely for 1D-only systems + +### 2. Define Types + +Use the convenience macros from `typedef.svh` to define all required types in one shot: + +```verilog +`include "idma/typedef.svh" + +// Define address, data, and ID types +typedef logic [AddrWidth-1:0] addr_t; +typedef logic [DataWidth-1:0] data_t; +typedef logic [IdWidth-1:0] id_t; +typedef logic [TFLenWidth-1:0] tf_len_t; + +// 1D request/response types (expands options_t and err_payload_t internally) +`IDMA_TYPEDEF_FULL_REQ_T(idma_req_t, id_t, addr_t, tf_len_t) +`IDMA_TYPEDEF_FULL_RSP_T(idma_rsp_t, addr_t) + +// ND request type (if using ND midend) +typedef logic [RepWidth-1:0] reps_t; +typedef logic [StrideWidth-1:0] strides_t; +`IDMA_TYPEDEF_FULL_ND_REQ_T(idma_nd_req_t, idma_req_t, reps_t, strides_t) +``` + +The `IDMA_TYPEDEF_FULL_REQ_T` macro is a convenience wrapper that internally invokes `IDMA_TYPEDEF_OPTIONS_T` and `IDMA_TYPEDEF_REQ_T`. Use the `FULL_` variants for integration — they define all intermediate types automatically. The non-`FULL_` macros (`IDMA_TYPEDEF_REQ_T`, `IDMA_TYPEDEF_OPTIONS_T`) define individual types and require you to provide the intermediate types manually. Use `FULL_` unless you need custom intermediate types. + +### 3. Instantiate + +All iDMA modules use a single clock (`clk_i`) and synchronous active-low reset (`rst_ni`). The clock must be the same for all three layers (frontend, midend, backend) and the attached memory system. + +Wire the three layers together. The key connections are: +- Frontend `dma_req_o` / `req_valid_o` / `req_ready_i` -> Midend ND request input +- Midend `burst_req_o` / `burst_req_valid_o` / `burst_req_ready_i` -> Backend request input +- Backend `idma_rsp_o` / `rsp_valid_o` / `rsp_ready_i` -> back through midend to frontend + +The following skeleton shows how the three layers connect. Signal types come from the macros defined in step 2 above — `fe_req` is `idma_nd_req_t`, `be_req` is `idma_req_t`: + +```verilog +// Frontend -> Midend -> Backend + +idma_reg64_2d #( + .NumRegs ( 1 ), + .NumStreams ( 1 ), + .reg_req_t ( reg_req_t ), + .reg_rsp_t ( reg_rsp_t ), + .dma_req_t ( idma_nd_req_t ) +) i_frontend ( + .clk_i, + .rst_ni, + .reg_req_i ( dma_reg_req ), + .reg_rsp_o ( dma_reg_rsp ), + .dma_req_o ( fe_req ), + .req_valid_o ( fe_valid ), + .req_ready_i ( fe_ready ), + .dma_rsp_i ( fe_rsp ), + .rsp_valid_i ( fe_rsp_valid ), + .rsp_ready_o ( fe_rsp_ready ) +); + +idma_nd_midend #( + .NumDim ( 2 ), + .addr_t ( addr_t ), + .idma_req_t ( idma_req_t ), + .idma_rsp_t ( idma_rsp_t ), + .idma_nd_req_t ( idma_nd_req_t ), + .RepWidths ( 32'd32 ) +) i_midend ( + .clk_i, + .rst_ni, + .nd_req_i ( fe_req ), + .nd_req_valid_i ( fe_valid ), + .nd_req_ready_o ( fe_ready ), + .nd_rsp_o ( fe_rsp ), + .nd_rsp_valid_o ( fe_rsp_valid ), + .nd_rsp_ready_i ( fe_rsp_ready ), + .burst_req_o ( be_req ), + .burst_req_valid_o ( be_valid ), + .burst_req_ready_i ( be_ready ), + .burst_rsp_i ( be_rsp ), + .burst_rsp_valid_i ( be_rsp_valid ), + .burst_rsp_ready_o ( be_rsp_ready ) +); + +idma_backend_rw_axi #( + .DataWidth ( DataWidth ), + .AddrWidth ( AddrWidth ), + .idma_req_t ( idma_req_t ), + .idma_rsp_t ( idma_rsp_t ), + .axi_req_t ( axi_req_t ), + .axi_rsp_t ( axi_rsp_t ) + // Bus ports — variant-specific, see generated module for full port list +) i_backend ( + .clk_i, + .rst_ni, + .idma_req_i ( be_req ), + .req_valid_i ( be_valid ), + .req_ready_o ( be_ready ), + .idma_rsp_o ( be_rsp ), + .rsp_valid_o ( be_rsp_valid ), + .rsp_ready_i ( be_rsp_ready ), + .busy_o ( busy ) + // AXI read/write ports omitted — variant-specific +); +``` + +### 4. Set Parameters + +Recommended parameter presets: + +| | Minimum Area | Balanced | High Throughput | +|---|-------------|----------|-----------------| +| `DataWidth` | 32 | 64 | 256–512 | +| `BufferDepth` | 2 | 3 | 3 | +| `NumAxInFlight` | 2 | 3 | 4–8 | +| `MemSysDepth` | 0 | 0 | 8–16 | +| `CombinedShifter` | 1 | 0 | 0 | +| `RAWCouplingAvail` | 0 | 1 | 1 | +| `HardwareLegalizer` | 0 | 1 | 1 | +| `ErrorCap` | `NO_ERROR_HANDLING` | `ERROR_HANDLING` | `ERROR_HANDLING` | + +**Minimum Area** sacrifices throughput for gate count — single shifter, no coupling, software legalization. **Balanced** adds hardware legalization and coupling for correct-by-default behavior. **High Throughput** uses deep FIFOs and wide buses to saturate memory bandwidth. + +:::caution[Parameter misconfiguration] +Setting `RAWCouplingAvail=1` on a mixed-protocol backend (e.g., `r_obi_w_axi`) where the write protocol has no AW channel will cause synthesis errors. Set `ErrorCap=ERROR_HANDLING` only on single-read/single-write AXI variants (`rw_axi`), or the design will `$fatal` during elaboration. +::: + +## Real-World Examples + +The following SoCs provide canonical integration examples spanning different bus protocols, data widths, and frontend styles. + +### Cheshire + +| | | +|---|---| +| **Repo** | [pulp-platform/cheshire](https://github.com/pulp-platform/cheshire) | +| **Frontend** | `idma_reg64_{1d,2d}` | +| **Midend** | ND (2D, conditional) | +| **Backend** | `rw_axi` | +| **Bus** | AXI4 | +| **Data Width** | 64-bit | +| **Key File** | [`hw/cheshire_idma_wrap.sv`](https://github.com/pulp-platform/cheshire/blob/main/hw/cheshire_idma_wrap.sv) | + +**Start here** if your SoC uses a CVA6 core with AXI4. Cheshire is a CVA6-based Linux-capable SoC built around an AXI4 fabric. Its iDMA instance supports conditional 1D/2D mode, making it a good reference for register-frontend integrations with optional multi-dimensional transfers. + +### Croc + +| | | +|---|---| +| **Repo** | [pulp-platform/croc](https://github.com/pulp-platform/croc) | +| **Frontend** | Custom OBI register interface | +| **Midend** | ND (2D) | +| **Backend** | `rw_obi` | +| **Bus** | OBI | +| **Data Width** | 32-bit | +| **Key File** | [`rtl/idma/croc_idma.sv`](https://github.com/pulp-platform/croc/blob/main/rtl/idma/croc_idma.sv) | + +**Start here** for a minimal OBI-based integration. Croc is a minimal OBI-based SoC with a custom register frontend — the smallest and simplest example. + +### Snitch Cluster + +| | | +|---|---| +| **Repo** | [pulp-platform/snitch_cluster](https://github.com/pulp-platform/snitch_cluster) | +| **Frontend** | inst64 (Xdma ISA) | +| **Midend** | ND | +| **Backend** | `rw_axi` | +| **Bus** | AXI4 | +| **Data Width** | 512-bit | +| **Key File** | [`hw/snitch_cluster/src/`](https://github.com/pulp-platform/snitch_cluster/tree/main/hw/snitch_cluster/src) | + +Reference for ISA-coupled DMA with wide (512-bit) data paths. The Snitch cluster uses a wide 512-bit data path with an ISA-coupled DMA on a dedicated core. Transfers are submitted via Xdma custom instructions, achieving single-cycle launch latency. + +### PULP Cluster + +| | | +|---|---| +| **Repo** | [pulp-platform/pulp_cluster](https://github.com/pulp-platform/pulp_cluster) | +| **Frontend** | `idma_reg32_2d_frontend` | +| **Midend** | ND (2D) | +| **Backend** | `rw_axi` | +| **Bus** | AXI4 | +| **Data Width** | 64-bit | +| **Key File** | [`rtl/idma_wrap.sv`](https://github.com/pulp-platform/pulp_cluster/blob/main/rtl/idma_wrap.sv) | + +Shows multi-core DMA sharing and the mchan/iDMA selection mechanism. The PULP cluster is a multi-core architecture with tightly-coupled data memory (TCDM). It uses a register-based 2D frontend and supports conditional selection between the legacy mchan DMA and iDMA via the `TARGET_MCHAN` parameter. + +## Dependency Management + +iDMA uses [Bender](https://github.com/pulp-platform/bender) for RTL dependency management. Add iDMA to your `Bender.yml` and run `bender update` to pull it and its transitive dependencies (`axi`, `common_cells`, `register_interface`, `obi`). Bender resolves the source file list for your build system — use `bender script vsim` for Questa or `bender script vcs` for VCS. diff --git a/doc/site/src/content/docs/guides/verification.md b/doc/site/src/content/docs/guides/verification.md new file mode 100644 index 00000000..0a274348 --- /dev/null +++ b/doc/site/src/content/docs/guides/verification.md @@ -0,0 +1,218 @@ +--- +title: Verification +description: Testbench architecture, job files, and simulation workflow for iDMA. +--- + +## Verification Overview + +iDMA uses a SystemVerilog testbench driven by **job files** that describe transfer sequences. The testbench compares hardware behavior against a byte-accurate golden model. Tests are run with Questa or VCS, with job files located in `jobs//`. + +For documentation quality checks, see [Docs Verification Plan](../docs-verification/). + +## Testbench Architecture + +### Key Components + +| Component | Location | Description | +|-----------|----------|-------------| +| `idma_test` package | `test/idma_test.sv` | Shared test infrastructure: job class, golden model, drivers | +| `tb_idma_backend_*` | `test/tpl/tb_idma_backend.sv.tpl` (generated) | Per-variant top-level testbench module | +| `tb_tasks.svh` | `test/include/tb_tasks.svh` | Protocol-specific memory access tasks, job file parser | + +### Golden Model + +The testbench uses a **golden model** — a software reference implementation that predicts the expected memory state after each DMA transfer. By comparing the hardware's actual memory writes against the model's predictions, the testbench detects functional bugs without requiring hand-written expected values. + +The `idma_model` class in `idma_test.sv` is a byte-addressed memory model that simulates DMA transfers at the byte granularity. It replicates the legalizer's burst splitting logic (page boundaries, maximum burst lengths) and error handling behavior (continue/abort semantics). After each transfer, the testbench compares the hardware memory state against the model's expected state to detect mismatches. The golden model uses the `max_src_len` and `max_dst_len` fields from the job file to configure burst splitting — these must match the protocol's actual limits for comparisons to pass. If `max_src_len`/`max_dst_len` don't match the protocol's actual burst limits, the golden model will split bursts differently than the hardware legalizer, causing false mismatches. + +## Job File Format + +Each job file contains one or more transfer descriptions, concatenated back-to-back. Each transfer is described by the following fields, one per line. + +The most important fields are `length`, `src_addr`, `dst_addr`, and the two `max_*_len` fields (which must match your protocol's actual burst limits). For a basic AXI test, set both protocols to 0, both max lengths to 256, and both decoupling flags to 0. + +### Fields + +| Line | Format | Field | Description | +|------|--------|-------|-------------| +| 1 | `%d` | `length` | Transfer length in bytes | +| 2 | `0x%x` | `src_addr` | Source address (hex) | +| 3 | `0x%x` | `dst_addr` | Destination address (hex) | +| 4 | `%d` | `src_protocol` | Source protocol enum (0=AXI, 1=OBI, ...) | +| 5 | `%d` | `dst_protocol` | Destination protocol enum | +| 6 | `%d` | `max_src_len` | Max source burst length in beats | +| 7 | `%d` | `max_dst_len` | Max destination burst length in beats | +| 8 | `%b` | `aw_decoupled` | AW decoupling flag (0 or 1) | +| 9 | `%b` | `rw_decoupled` | RW decoupling flag (0 or 1) | +| 10 | `%d` | `num_errors` | Number of injected errors (0 for clean transfers) | +| 11+ | `%c%c0x%h` | error specs | One line per error: `r`/`w` + `c`/`a` + hex address | + +Error spec format: first character is `r` (read) or `w` (write), second is `c` (continue) or `a` (abort), followed by the error address in hex. + +### Example + +Annotated `simple.txt` (a single 2-byte transfer with no errors): + +``` +2 # length: 2 bytes +0x0 # src_addr: 0x000 +0x3ff # dst_addr: 0x3ff +0 # src_protocol: AXI (0) +0 # dst_protocol: AXI (0) +256 # max_src_len: 256 beats +256 # max_dst_len: 256 beats +0 # aw_decoupled: no +0 # rw_decoupled: no +0 # num_errors: 0 +``` + +Annotated error transfer (from `error_simple.txt`): + +``` +32 # length: 32 bytes +0x0 # src_addr +0x10000 # dst_addr +0 # AXI read +0 # AXI write +256 # max 256 beats +256 # max 256 beats +0 # aw_decoupled: no +0 # rw_decoupled: no +3 # 3 injected errors: +rc0x4 # read error at 0x4, action: continue +rc0x8 # read error at 0x8, action: continue +rc0xc # read error at 0xc, action: continue +``` + +### Writing Custom Job Files + +To create a custom test, write a text file following the format above. Each field is on its own line, with transfers concatenated back-to-back (no blank lines between them). The `max_src_len` and `max_dst_len` fields control burst splitting in the golden model — set to 256 for AXI (matching the protocol maximum) or 1 for single-beat protocols (OBI, INIT, AXI Stream). + +Here is an example with two back-to-back transfers in a single job file (64 bytes followed by 128 bytes, no errors): + +``` +64 +0x0 +0x1000 +0 +0 +256 +256 +0 +0 +0 +128 +0x100 +0x2000 +0 +0 +256 +256 +1 +0 +0 +``` + +## Available Test Suites + +Each backend variant has its own set of job files under `jobs//`: + +**Basic** — start here for bring-up and sanity checks: + +| Job File | Description | +|----------|-------------| +| `simple.txt` | Minimal transfer (2 bytes), basic sanity check | +| `small.txt` | A few short transfers | +| `tiny.txt` | Very small (sub-word) transfers | + +**Stress** — increasing transfer sizes for throughput and boundary testing: + +| Job File | Description | +|----------|-------------| +| `medium.txt` | Mixed lengths, some with AW decoupling | +| `large.txt` | Longer transfers approaching page boundaries | +| `huge.txt` | Large transfers spanning multiple pages | + +**Pattern** — specific address and access patterns: + +| Job File | Description | +|----------|-------------| +| `linear.txt` | Sequential address patterns | +| `mixed.txt` | Varied source/destination alignments | +| `same_dst.txt` | Multiple transfers to the same destination | +| `zero_transfer.txt` | Zero-length transfer (tests `RejectZeroTransfers`) | + +**Error** — error injection and handling: + +| Job File | Description | +|----------|-------------| +| `error_simple.txt` | Transfers with injected read/write errors and continue/abort actions | +| `error_mixed.txt` | Complex error scenarios with multiple error types | + +For initial bring-up, start with `simple.txt` on the `rw_axi` variant — it's the smallest test on the most common backend. + +:::note[Figure placeholder] +Diagram: verification testbench architecture. +Show job parser feeding the DUT wrapper, simulated memory, and golden model checker. +::: + +## Running Simulations + +### Prerequisites + +Before running any simulation, generate the RTL and simulation scripts: + +```bash +make idma_hw_all # Generate RTL into target/rtl/ +make idma_sim_all # Generate compile.tcl and start.tcl into target/sim/vsim/ +``` + +### Compile + +Compile the generated design with Questa: + +```bash +cd target/sim/vsim +questa-2023.4 vsim -c -do "source compile.tcl; quit" +``` + +### Run + +Run a simulation against a specific job file: + +```bash +questa-2023.4 vsim -c -t 1ps -voptargs=+acc \ + +job_file=../../../jobs/backend_rw_axi/simple.txt \ + -logfile output.log \ + tb_idma_backend_rw_axi \ + -do "source start.tcl; run -all" +``` + +Replace `backend_rw_axi` and `tb_idma_backend_rw_axi` with the desired variant. The `+job_file` plusarg points to the job file describing the test sequence. + +### Debugging Failures + +If a simulation fails, the testbench prints the first mismatching address and expected vs. actual values. To debug further, open the waveform in the Questa GUI by removing the `-c` flag from the vsim command. + +Check the `busy_o` flags to identify which subunit stalled: + +| Flag | Stuck means | +|------|-------------| +| `r_leg_busy` | Legalizer can't split — check transfer parameters | +| `r_dp_busy` | Read channel not getting responses — check memory slave | +| `buffer_busy` | Write channel not draining — check write backpressure | +| `w_dp_busy` | Write channel blocked — check destination memory | +| `eh_fsm_busy` | Error handler waiting for software action | + +Key signals to trace in waveforms: `idma_req_i`/`req_valid_i`/`req_ready_o` (request handshake), `idma_rsp_o`/`rsp_valid_o` (response), `busy_o` (subunit status), and the AXI AR/AW/R/W/B channels on the bus interface. + +### VCS + +Simulation scripts for VCS are generated alongside Questa scripts via `make idma_sim_all`. The flow is analogous — compile with the generated script, then run with the `+job_file` plusarg. + +## Source Files + +- `test/idma_test.sv` — Test package (job class, golden model, drivers) +- `test/tpl/tb_idma_backend.sv.tpl` — Testbench template (generates per-variant TBs) +- `test/include/tb_tasks.svh` — Memory tasks, job parser (`read_jobs`) +- `jobs/` — Job files organized by backend variant diff --git a/doc/site/src/content/docs/index.md b/doc/site/src/content/docs/index.md new file mode 100644 index 00000000..8d28fabb --- /dev/null +++ b/doc/site/src/content/docs/index.md @@ -0,0 +1,66 @@ +--- +title: iDMA +description: A modular DMA engine for heterogeneous PULP-platform SoCs. +--- + +## What iDMA Is + +iDMA moves data between memories and peripherals across different bus protocols (AXI, OBI, TileLink) and supports multi-dimensional transfers. It splits the problem into three layers so you can mix and match integration styles without changing the core engine. + +- **Frontend**: software-visible interface for requests. +- **Midend**: optional ND/RT decomposition. +- **Backend**: protocol execution on the bus. + +![Architecture Overview](/fig/architecture_overview.svg) + +:::note[Figure placeholder] +Diagram: end-to-end request lifecycle (frontend request, optional midend split, backend legalizer + transport, response). +Show where `idma_req_t` and `idma_rsp_t` are created and consumed. +::: + +## Start Here + +If you are integrating iDMA into an SoC, read these in order: + +- [Quickstart](./guides/quickstart/) +- [Programming Model](./architecture/programming-model/) +- [System Integration](./guides/system-integration/) + +If you are deep-diving the design: + +- [Frontend](./architecture/frontend/) +- [Midend](./architecture/midend/) +- [Backend](./architecture/backend/) +- [Interfaces and Types](./architecture/interfaces/) + +## Supported Protocols + +The backend supports these protocols via `protocol_e` in `idma_pkg.sv`: + +| Enum Value | Protocol | Description | Typical Use | +|------------|----------|-------------|-------------| +| 0 | `AXI` | Full AXI4 | Main memory, high bandwidth | +| 1 | `OBI` | OBI | Simple peripherals, low area | +| 2 | `AXILITE` | AXI4-Lite | Register access | +| 3 | `TILELINK` | TileLink-UH | TL-based SoCs (via TLToAXI4) | +| 4 | `INIT` | Init protocol | Efficient zeroing (Occamy) | +| 5 | `AXI_STREAM` | AXI Stream | Streaming endpoints | + +## Code Generation (High Level) + +iDMA uses the MARIO generator to produce protocol-specific RTL from templates and YAML capability databases. This is how a single codebase produces many backend variants. + +Key locations: + +- `src/db/*.yml` — protocol capability databases +- `src/backend/tpl/` — backend templates +- `src/frontend/tpl/` — register frontend templates +- `util/gen_idma.py` — generator entry point +- `util/mario/` — generator modules + +## Where to Find Details + +- Full data type definitions: [Interfaces and Types](./architecture/interfaces/) +- Performance constraints and tradeoffs: [Performance and Limitations](./guides/performance-limitations/) +- Testbench and job files: [Verification](./guides/verification/) +- Documentation QA checklist: [Docs Verification Plan](./guides/docs-verification/) diff --git a/doc/site/tsconfig.json b/doc/site/tsconfig.json new file mode 100644 index 00000000..bcbf8b50 --- /dev/null +++ b/doc/site/tsconfig.json @@ -0,0 +1,3 @@ +{ + "extends": "astro/tsconfigs/strict" +}