diff --git a/hw/top_chip/dv/mocha_sim_cfgs.hjson b/hw/top_chip/dv/mocha_sim_cfgs.hjson
index df6e44a61..506d07d2f 100644
--- a/hw/top_chip/dv/mocha_sim_cfgs.hjson
+++ b/hw/top_chip/dv/mocha_sim_cfgs.hjson
@@ -30,6 +30,7 @@
     "{proj_root}/hw/vendor/lowrisc_ip/ip/i2c/dv/i2c_sim_cfg.hjson",
     "{proj_root}/hw/top_chip/ip/xbar_peri/dv/autogen/xbar_peri_sim_cfg.hjson",
     "{proj_root}/hw/top_chip/ip_autogen/gpio/dv/gpio_sim_cfg.hjson",
+    "{proj_root}/hw/top_chip/ip_autogen/rstmgr/dv/rstmgr_sim_cfg.hjson",
     "{proj_root}/hw/vendor/lowrisc_ip/ip/rom_ctrl/dv/rom_ctrl_32kB_sim_cfg.hjson",
     "{proj_root}/hw/top_chip/tmp_sim_cfg/rv_dm_use_jtag_interface_sim_cfg.hjson",
 
diff --git a/hw/top_chip/ip_autogen/rstmgr/data/rstmgr_testplan.hjson b/hw/top_chip/ip_autogen/rstmgr/data/rstmgr_testplan.hjson
index be44e83d0..0fdfd521a 100644
--- a/hw/top_chip/ip_autogen/rstmgr/data/rstmgr_testplan.hjson
+++ b/hw/top_chip/ip_autogen/rstmgr/data/rstmgr_testplan.hjson
@@ -3,12 +3,12 @@
 // SPDX-License-Identifier: Apache-2.0
 {
   name: "rstmgr"
-  import_testplans: ["hw/dv/tools/dvsim/testplans/alert_test_testplan.hjson",
-                     "hw/dv/tools/dvsim/testplans/csr_testplan.hjson",
-                     "hw/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson",
-                     "hw/dv/tools/dvsim/testplans/stress_all_with_reset_testplan.hjson",
-                     "hw/dv/tools/dvsim/testplans/sec_cm_count_testplan.hjson",
-                     "hw/dv/tools/dvsim/testplans/sec_cm_fsm_testplan.hjson",
+  import_testplans: ["hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/alert_test_testplan.hjson",
+                     "hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/csr_testplan.hjson",
+                     "hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson",
+                     "hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/stress_all_with_reset_testplan.hjson",
+                     "hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/sec_cm_count_testplan.hjson",
+                     "hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/sec_cm_fsm_testplan.hjson",
                      "rstmgr_sec_cm_testplan.hjson"]
 
   testpoints: [
diff --git a/hw/top_chip/ip_autogen/rstmgr/dv/env/rstmgr_if.sv b/hw/top_chip/ip_autogen/rstmgr/dv/env/rstmgr_if.sv
index 900be51d5..b78aa7bd4 100644
--- a/hw/top_chip/ip_autogen/rstmgr/dv/env/rstmgr_if.sv
+++ b/hw/top_chip/ip_autogen/rstmgr/dv/env/rstmgr_if.sv
@@ -65,5 +65,5 @@ interface rstmgr_if (
   always_comb cpu_info_en = `PATH_TO_DUT.reg2hw.cpu_info_ctrl.en.q;
 
   bit rst_ni_inactive;
-  always_comb rst_ni_inactive = resets_o.rst_lc_io_n[rstmgr_pkg::DomainMainSel];
+  always_comb rst_ni_inactive = resets_o.rst_io_n[rstmgr_pkg::DomainMainSel];
 endinterface
diff --git a/hw/top_chip/ip_autogen/rstmgr/dv/env/seq_lib/rstmgr_reset_vseq.sv b/hw/top_chip/ip_autogen/rstmgr/dv/env/seq_lib/rstmgr_reset_vseq.sv
index 0cbca2754..f1e5d9c74 100644
--- a/hw/top_chip/ip_autogen/rstmgr/dv/env/seq_lib/rstmgr_reset_vseq.sv
+++ b/hw/top_chip/ip_autogen/rstmgr/dv/env/seq_lib/rstmgr_reset_vseq.sv
@@ -115,8 +115,8 @@ class rstmgr_reset_vseq extends rstmgr_base_vseq;
     expected_cpu_enable = 0;
 
     cfg.clk_rst_vif.wait_clks(8);
-    // Wait till rst_lc_n is inactive for non-aon.
-    `DV_WAIT(cfg.rstmgr_vif.resets_o.rst_lc_n[1])
+    // Wait till rst_io_n is inactive for non-aon.
+    `DV_WAIT(cfg.rstmgr_vif.resets_o.rst_io_n[1])
 
     check_reset_info(get_reset_code(start_reset, 0), {reset_name[start_reset], " reset"});
     check_alert_info_after_reset(expected_alert_dump, expected_alert_enable);
@@ -172,7 +172,7 @@ class rstmgr_reset_vseq extends rstmgr_base_vseq;
       reset_done();
 
       cfg.io_clk_rst_vif.wait_clks(8);
-      wait(cfg.rstmgr_vif.resets_o.rst_lc_n[1]);
+      wait(cfg.rstmgr_vif.resets_o.rst_io_n[1]);
       check_reset_info(expected_reset_info_code);
       check_alert_info_after_reset(.alert_dump(expected_alert_dump),
                                    .enable(expected_alert_enable));
diff --git a/hw/top_chip/ip_autogen/rstmgr/dv/rstmgr_cnsty_chk/rstmgr_cnsty_chk_sim_cfg.hjson b/hw/top_chip/ip_autogen/rstmgr/dv/rstmgr_cnsty_chk/rstmgr_cnsty_chk_sim_cfg.hjson
index 65e497ee2..dc56da856 100644
--- a/hw/top_chip/ip_autogen/rstmgr/dv/rstmgr_cnsty_chk/rstmgr_cnsty_chk_sim_cfg.hjson
+++ b/hw/top_chip/ip_autogen/rstmgr/dv/rstmgr_cnsty_chk/rstmgr_cnsty_chk_sim_cfg.hjson
@@ -21,7 +21,7 @@
   testplan: "{self_dir}/data/rstmgr_cnsty_chk_testplan.hjson"
 
   // Import additional common sim cfg files.
-  import_cfgs: ["{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson"]
+  import_cfgs: ["{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/common_sim_cfg.hjson"]
 
 
   // Specific exclusion files.
diff --git a/hw/top_chip/ip_autogen/rstmgr/dv/rstmgr_sim_cfg.hjson b/hw/top_chip/ip_autogen/rstmgr/dv/rstmgr_sim_cfg.hjson
index 62fab1652..b9ebabb79 100644
--- a/hw/top_chip/ip_autogen/rstmgr/dv/rstmgr_sim_cfg.hjson
+++ b/hw/top_chip/ip_autogen/rstmgr/dv/rstmgr_sim_cfg.hjson
@@ -12,7 +12,7 @@
   tb: tb
 
   // Simulator used to sign off this block
-  tool: vcs
+  tool: xcelium
 
   // Fusesoc core file used for building the file list.
   fusesoc_core: lowrisc:mocha_dv:rstmgr_sim:0.1
@@ -25,16 +25,16 @@
 
   // Import additional common sim cfg files.
   import_cfgs: [// Project wide common sim cfg file
-                "{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson",
+                "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/common_sim_cfg.hjson",
                 // Common CIP test lists
-                "{proj_root}/hw/dv/tools/dvsim/tests/csr_tests.hjson",
-                "{proj_root}/hw/dv/tools/dvsim/tests/alert_test.hjson",
-                "{proj_root}/hw/dv/tools/dvsim/tests/tl_access_tests.hjson",
-                "{proj_root}/hw/dv/tools/dvsim/tests/sec_cm_tests.hjson",
+                "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/csr_tests.hjson",
+                "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/alert_test.hjson",
+                "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/tl_access_tests.hjson",
+                "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/sec_cm_tests.hjson",
                 // Just run the stress_all sequence, and don't inject random
                 // resets since we may get overlapping resets due to sequences
                 // that inject them.
-                "{proj_root}/hw/dv/tools/dvsim/tests/stress_all_test.hjson"
+                "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/stress_all_test.hjson"
                 ]
 
   // Specific exclusion files.
diff --git a/hw/top_chip/ip_autogen/rstmgr/dv/sva/rstmgr_cascading_sva_if.sv b/hw/top_chip/ip_autogen/rstmgr/dv/sva/rstmgr_cascading_sva_if.sv
index a81fa6f46..e71890760 100644
--- a/hw/top_chip/ip_autogen/rstmgr/dv/sva/rstmgr_cascading_sva_if.sv
+++ b/hw/top_chip/ip_autogen/rstmgr/dv/sva/rstmgr_cascading_sva_if.sv
@@ -158,17 +158,21 @@ interface rstmgr_cascading_sva_if (
   `CASCADED_ASSERTS(CascadeEffAonToRstPorMain, effective_aon_rst_n[rstmgr_pkg::DomainAonSel],
                     resets_o.rst_por_n[rstmgr_pkg::DomainAonSel], SyncCycles, clk_main_i)
 
-  // Controlled by rst_lc_src_n.
-  `CASCADED_ASSERTS(CascadeLcToLcAon, rst_lc_src_n[rstmgr_pkg::DomainAonSel],
-                    resets_o.rst_lc_aon_n[rstmgr_pkg::DomainAonSel], SysCycles, clk_aon_i)
-  `CASCADED_ASSERTS(CascadeLcToLc, rst_lc_src_n[rstmgr_pkg::DomainMainSel],
-                    resets_o.rst_lc_n[rstmgr_pkg::DomainMainSel], SysCycles, clk_main_i)
-
   // Controlled by rst_sys_src_n.
-  `CASCADED_ASSERTS(CascadeSysToSys, rst_sys_src_n[rstmgr_pkg::DomainMainSel],
-                    resets_o.rst_sys_n[rstmgr_pkg::DomainMainSel], PeriCycles, clk_main_i)
-  `CASCADED_ASSERTS(CascadeLcToLcShadowed, rst_lc_src_n[rstmgr_pkg::DomainMainSel],
-                    resets_o.rst_lc_shadowed_n[rstmgr_pkg::DomainMainSel], SysCycles, clk_main_i)
+  `CASCADED_ASSERTS(CascadeSysToMain_A, rst_sys_src_n[rstmgr_pkg::DomainMainSel],
+                    resets_o.rst_main_n[rstmgr_pkg::DomainMainSel], PeriCycles, clk_main_i)
+
+  `CASCADED_ASSERTS(CascadeSysToIO_A, rst_sys_src_n[rstmgr_pkg::DomainMainSel],
+                    resets_o.rst_io_n[rstmgr_pkg::DomainMainSel], PeriCycles, clk_io_i)
+
+  `CASCADED_ASSERTS(CascadeSysToSPIHost_A, rst_sys_src_n[rstmgr_pkg::DomainMainSel],
+                    resets_o.rst_spi_host_n[rstmgr_pkg::DomainMainSel], PeriCycles, clk_io_i)
+
+  `CASCADED_ASSERTS(CascadeSysToSPIDevice_A, rst_sys_src_n[rstmgr_pkg::DomainMainSel],
+                    resets_o.rst_spi_device_n[rstmgr_pkg::DomainMainSel], PeriCycles, clk_io_i)
+
+  `CASCADED_ASSERTS(CascadeSysToI2C_A, rst_sys_src_n[rstmgr_pkg::DomainMainSel],
+                    resets_o.rst_i2c_n[rstmgr_pkg::DomainMainSel], PeriCycles, clk_io_i)
 
   `undef FALL_ASSERT
   `undef RISE_ASSERTS
diff --git a/hw/top_chip/ip_autogen/rstmgr/dv/tb.sv b/hw/top_chip/ip_autogen/rstmgr/dv/tb.sv
index 8ca92c45a..b41d8bfac 100644
--- a/hw/top_chip/ip_autogen/rstmgr/dv/tb.sv
+++ b/hw/top_chip/ip_autogen/rstmgr/dv/tb.sv
@@ -40,7 +40,7 @@ module tb;
 
   tl_if tl_if (
     .clk,
-    .rst_n(rstmgr_if.resets_o.rst_lc_io_n[rstmgr_pkg::DomainMainSel])
+    .rst_n(rstmgr_if.resets_o.rst_io_n[rstmgr_pkg::DomainMainSel])
   );
 
   rstmgr_if rstmgr_if (
@@ -63,7 +63,7 @@ module tb;
   // This is consistent with rstmgr being the only source of resets.
   rstmgr dut (
     .clk_i        (clk),
-    .rst_ni       (rstmgr_if.resets_o.rst_lc_io_n[rstmgr_pkg::DomainMainSel]),
+    .rst_ni       (rstmgr_if.resets_o.rst_io_n[rstmgr_pkg::DomainMainSel]),
     .clk_aon_i    (clk_aon),
     .clk_io_i     (clk_io),
     .clk_main_i   (clk_main),
@@ -118,7 +118,7 @@ module tb;
     // This may help any code that depends on clk_rst_vif.rst_n in the infrastructure: they won't
     // be able to change but at least the reset value will be true to the environment.
     clk_rst_if.drive_rst_n = 1'b0;
-    force clk_rst_if.rst_n = rstmgr_if.resets_o.rst_lc_io_n[rstmgr_pkg::DomainMainSel];
+    force clk_rst_if.rst_n = rstmgr_if.resets_o.rst_io_n[rstmgr_pkg::DomainMainSel];
   end
 
 endmodule
diff --git a/hw/vendor/lowrisc_ip.vendor.hjson b/hw/vendor/lowrisc_ip.vendor.hjson
index 140000d75..840f601d0 100644
--- a/hw/vendor/lowrisc_ip.vendor.hjson
+++ b/hw/vendor/lowrisc_ip.vendor.hjson
@@ -45,7 +45,7 @@
     {from: "hw/ip_templates/clkmgr",        to: "ip_templates/clkmgr"},
     {from: "hw/ip_templates/gpio",          to: "ip_templates/gpio", patch_dir: "gpio"}, // General purpose I/O
     {from: "hw/ip_templates/pwrmgr",        to: "ip_templates/pwrmgr", patch_dir: "pwrmgr"},
-    {from: "hw/ip_templates/rstmgr",        to: "ip_templates/rstmgr"},
+    {from: "hw/ip_templates/rstmgr",        to: "ip_templates/rstmgr", patch_dir: "rstmgr"},
     {from: "hw/ip_templates/rv_plic",       to: "ip_templates/rv_plic"},
 
     // Primitives.
diff --git a/hw/vendor/lowrisc_ip/ip_templates/rstmgr/data/rstmgr_testplan.hjson b/hw/vendor/lowrisc_ip/ip_templates/rstmgr/data/rstmgr_testplan.hjson
index be44e83d0..0fdfd521a 100644
--- a/hw/vendor/lowrisc_ip/ip_templates/rstmgr/data/rstmgr_testplan.hjson
+++ b/hw/vendor/lowrisc_ip/ip_templates/rstmgr/data/rstmgr_testplan.hjson
@@ -3,12 +3,12 @@
 // SPDX-License-Identifier: Apache-2.0
 {
   name: "rstmgr"
-  import_testplans: ["hw/dv/tools/dvsim/testplans/alert_test_testplan.hjson",
-                     "hw/dv/tools/dvsim/testplans/csr_testplan.hjson",
-                     "hw/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson",
-                     "hw/dv/tools/dvsim/testplans/stress_all_with_reset_testplan.hjson",
-                     "hw/dv/tools/dvsim/testplans/sec_cm_count_testplan.hjson",
-                     "hw/dv/tools/dvsim/testplans/sec_cm_fsm_testplan.hjson",
+  import_testplans: ["hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/alert_test_testplan.hjson",
+                     "hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/csr_testplan.hjson",
+                     "hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson",
+                     "hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/stress_all_with_reset_testplan.hjson",
+                     "hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/sec_cm_count_testplan.hjson",
+                     "hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/sec_cm_fsm_testplan.hjson",
                      "rstmgr_sec_cm_testplan.hjson"]
 
   testpoints: [
diff --git a/hw/vendor/lowrisc_ip/ip_templates/rstmgr/dv/env/rstmgr_if.sv.tpl b/hw/vendor/lowrisc_ip/ip_templates/rstmgr/dv/env/rstmgr_if.sv.tpl
index cb2102d9e..25c6fe26a 100644
--- a/hw/vendor/lowrisc_ip/ip_templates/rstmgr/dv/env/rstmgr_if.sv.tpl
+++ b/hw/vendor/lowrisc_ip/ip_templates/rstmgr/dv/env/rstmgr_if.sv.tpl
@@ -13,7 +13,7 @@ elif "io" in all_clks:
 else:
     assert 0, "No preferred clock available"
 
-preferred_rst_n = f"rst_lc_{preferred_domain}_n"
+preferred_rst_n = f"rst_{preferred_domain}_n"
 %>\
 
 interface rstmgr_if (
diff --git a/hw/vendor/lowrisc_ip/ip_templates/rstmgr/dv/env/seq_lib/rstmgr_reset_vseq.sv.tpl b/hw/vendor/lowrisc_ip/ip_templates/rstmgr/dv/env/seq_lib/rstmgr_reset_vseq.sv.tpl
index 356807f65..1670853b0 100644
--- a/hw/vendor/lowrisc_ip/ip_templates/rstmgr/dv/env/seq_lib/rstmgr_reset_vseq.sv.tpl
+++ b/hw/vendor/lowrisc_ip/ip_templates/rstmgr/dv/env/seq_lib/rstmgr_reset_vseq.sv.tpl
@@ -127,8 +127,8 @@ class rstmgr_reset_vseq extends rstmgr_base_vseq;
     expected_cpu_enable = 0;
 
     cfg.clk_rst_vif.wait_clks(8);
-    // Wait till rst_lc_n is inactive for non-aon.
-    `DV_WAIT(cfg.rstmgr_vif.resets_o.rst_lc_n[1])
+    // Wait till rst_io_n is inactive for non-aon.
+    `DV_WAIT(cfg.rstmgr_vif.resets_o.rst_io_n[1])
 
     check_reset_info(get_reset_code(start_reset, 0), {reset_name[start_reset], " reset"});
     check_alert_info_after_reset(expected_alert_dump, expected_alert_enable);
@@ -184,7 +184,7 @@ class rstmgr_reset_vseq extends rstmgr_base_vseq;
       reset_done();
 
       cfg.${preferred_clk_rst_vif}.wait_clks(8);
-      wait(cfg.rstmgr_vif.resets_o.rst_lc_n[1]);
+      wait(cfg.rstmgr_vif.resets_o.rst_io_n[1]);
       check_reset_info(expected_reset_info_code);
       check_alert_info_after_reset(.alert_dump(expected_alert_dump),
                                    .enable(expected_alert_enable));
diff --git a/hw/vendor/lowrisc_ip/ip_templates/rstmgr/dv/rstmgr_cnsty_chk/rstmgr_cnsty_chk_sim_cfg.hjson.tpl b/hw/vendor/lowrisc_ip/ip_templates/rstmgr/dv/rstmgr_cnsty_chk/rstmgr_cnsty_chk_sim_cfg.hjson.tpl
index 42f8b2258..1107fe81b 100644
--- a/hw/vendor/lowrisc_ip/ip_templates/rstmgr/dv/rstmgr_cnsty_chk/rstmgr_cnsty_chk_sim_cfg.hjson.tpl
+++ b/hw/vendor/lowrisc_ip/ip_templates/rstmgr/dv/rstmgr_cnsty_chk/rstmgr_cnsty_chk_sim_cfg.hjson.tpl
@@ -21,7 +21,7 @@
   testplan: "{self_dir}/data/rstmgr_cnsty_chk_testplan.hjson"
 
   // Import additional common sim cfg files.
-  import_cfgs: ["{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson"]
+  import_cfgs: ["{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/common_sim_cfg.hjson"]
 
 
   // Specific exclusion files.
diff --git a/hw/vendor/lowrisc_ip/ip_templates/rstmgr/dv/rstmgr_sim_cfg.hjson.tpl b/hw/vendor/lowrisc_ip/ip_templates/rstmgr/dv/rstmgr_sim_cfg.hjson.tpl
index b12e73af8..3c504393c 100644
--- a/hw/vendor/lowrisc_ip/ip_templates/rstmgr/dv/rstmgr_sim_cfg.hjson.tpl
+++ b/hw/vendor/lowrisc_ip/ip_templates/rstmgr/dv/rstmgr_sim_cfg.hjson.tpl
@@ -12,7 +12,7 @@
   tb: tb
 
   // Simulator used to sign off this block
-  tool: vcs
+  tool: xcelium
 
   // Fusesoc core file used for building the file list.
   fusesoc_core: ${instance_vlnv("lowrisc:dv:rstmgr_sim:0.1")}
@@ -25,16 +25,16 @@
 
   // Import additional common sim cfg files.
   import_cfgs: [// Project wide common sim cfg file
-                "{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson",
+                "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/common_sim_cfg.hjson",
                 // Common CIP test lists
-                "{proj_root}/hw/dv/tools/dvsim/tests/csr_tests.hjson",
-                "{proj_root}/hw/dv/tools/dvsim/tests/alert_test.hjson",
-                "{proj_root}/hw/dv/tools/dvsim/tests/tl_access_tests.hjson",
-                "{proj_root}/hw/dv/tools/dvsim/tests/sec_cm_tests.hjson",
+                "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/csr_tests.hjson",
+                "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/alert_test.hjson",
+                "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/tl_access_tests.hjson",
+                "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/sec_cm_tests.hjson",
                 // Just run the stress_all sequence, and don't inject random
                 // resets since we may get overlapping resets due to sequences
                 // that inject them.
-                "{proj_root}/hw/dv/tools/dvsim/tests/stress_all_test.hjson"
+                "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/stress_all_test.hjson"
                 ]
 
   // Specific exclusion files.
diff --git a/hw/vendor/lowrisc_ip/ip_templates/rstmgr/dv/sva/rstmgr_cascading_sva_if.sv.tpl b/hw/vendor/lowrisc_ip/ip_templates/rstmgr/dv/sva/rstmgr_cascading_sva_if.sv.tpl
index 143d0ed5b..1653cb608 100644
--- a/hw/vendor/lowrisc_ip/ip_templates/rstmgr/dv/sva/rstmgr_cascading_sva_if.sv.tpl
+++ b/hw/vendor/lowrisc_ip/ip_templates/rstmgr/dv/sva/rstmgr_cascading_sva_if.sv.tpl
@@ -183,17 +183,21 @@ interface rstmgr_cascading_sva_if (
                     resets_o.rst_por_${clk + "_" if clk != "main" else ""}n[rstmgr_pkg::DomainAonSel], SyncCycles, clk_${clk}_i)
 % endfor
 
-  // Controlled by rst_lc_src_n.
-  `CASCADED_ASSERTS(CascadeLcToLcAon, rst_lc_src_n[rstmgr_pkg::DomainAonSel],
-                    resets_o.rst_lc_aon_n[rstmgr_pkg::DomainAonSel], SysCycles, clk_aon_i)
-  `CASCADED_ASSERTS(CascadeLcToLc, rst_lc_src_n[rstmgr_pkg::DomainMainSel],
-                    resets_o.rst_lc_n[rstmgr_pkg::DomainMainSel], SysCycles, clk_main_i)
-
   // Controlled by rst_sys_src_n.
-  `CASCADED_ASSERTS(CascadeSysToSys, rst_sys_src_n[rstmgr_pkg::DomainMainSel],
-                    resets_o.rst_sys_n[rstmgr_pkg::DomainMainSel], PeriCycles, clk_main_i)
-  `CASCADED_ASSERTS(CascadeLcToLcShadowed, rst_lc_src_n[rstmgr_pkg::DomainMainSel],
-                    resets_o.rst_lc_shadowed_n[rstmgr_pkg::DomainMainSel], SysCycles, clk_main_i)
+  `CASCADED_ASSERTS(CascadeSysToMain_A, rst_sys_src_n[rstmgr_pkg::DomainMainSel],
+                    resets_o.rst_main_n[rstmgr_pkg::DomainMainSel], PeriCycles, clk_main_i)
+
+  `CASCADED_ASSERTS(CascadeSysToIO_A, rst_sys_src_n[rstmgr_pkg::DomainMainSel],
+                    resets_o.rst_io_n[rstmgr_pkg::DomainMainSel], PeriCycles, clk_io_i)
+
+  `CASCADED_ASSERTS(CascadeSysToSPIHost_A, rst_sys_src_n[rstmgr_pkg::DomainMainSel],
+                    resets_o.rst_spi_host_n[rstmgr_pkg::DomainMainSel], PeriCycles, clk_io_i)
+
+  `CASCADED_ASSERTS(CascadeSysToSPIDevice_A, rst_sys_src_n[rstmgr_pkg::DomainMainSel],
+                    resets_o.rst_spi_device_n[rstmgr_pkg::DomainMainSel], PeriCycles, clk_io_i)
+
+  `CASCADED_ASSERTS(CascadeSysToI2C_A, rst_sys_src_n[rstmgr_pkg::DomainMainSel],
+                    resets_o.rst_i2c_n[rstmgr_pkg::DomainMainSel], PeriCycles, clk_io_i)
 
   `undef FALL_ASSERT
   `undef RISE_ASSERTS
diff --git a/hw/vendor/lowrisc_ip/ip_templates/rstmgr/dv/tb.sv.tpl b/hw/vendor/lowrisc_ip/ip_templates/rstmgr/dv/tb.sv.tpl
index c2e8ce4eb..49dbb579b 100644
--- a/hw/vendor/lowrisc_ip/ip_templates/rstmgr/dv/tb.sv.tpl
+++ b/hw/vendor/lowrisc_ip/ip_templates/rstmgr/dv/tb.sv.tpl
@@ -12,7 +12,7 @@ elif "io" in all_clks:
 else:
     assert 0, "No preferred clock available"
 
-preferred_rst_n = f"rst_lc_{preferred_domain}_n"
+preferred_rst_n = f"rst_{preferred_domain}_n"
 preferred_por_n = f"rst_por_{preferred_domain}_n"
 %>\
 module tb;
diff --git a/hw/vendor/patches/lowrisc_ip/rstmgr/0001_Fix_Paths_And_Tools.patch b/hw/vendor/patches/lowrisc_ip/rstmgr/0001_Fix_Paths_And_Tools.patch
new file mode 100644
index 000000000..6e545a611
--- /dev/null
+++ b/hw/vendor/patches/lowrisc_ip/rstmgr/0001_Fix_Paths_And_Tools.patch
@@ -0,0 +1,73 @@
+diff --git a/data/rstmgr_testplan.hjson b/data/rstmgr_testplan.hjson
+index be44e83..0fdfd52 100644
+--- a/data/rstmgr_testplan.hjson
++++ b/data/rstmgr_testplan.hjson
+@@ -3,12 +3,12 @@
+ // SPDX-License-Identifier: Apache-2.0
+ {
+   name: "rstmgr"
+-  import_testplans: ["hw/dv/tools/dvsim/testplans/alert_test_testplan.hjson",
+-                     "hw/dv/tools/dvsim/testplans/csr_testplan.hjson",
+-                     "hw/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson",
+-                     "hw/dv/tools/dvsim/testplans/stress_all_with_reset_testplan.hjson",
+-                     "hw/dv/tools/dvsim/testplans/sec_cm_count_testplan.hjson",
+-                     "hw/dv/tools/dvsim/testplans/sec_cm_fsm_testplan.hjson",
++  import_testplans: ["hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/alert_test_testplan.hjson",
++                     "hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/csr_testplan.hjson",
++                     "hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson",
++                     "hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/stress_all_with_reset_testplan.hjson",
++                     "hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/sec_cm_count_testplan.hjson",
++                     "hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/sec_cm_fsm_testplan.hjson",
+                      "rstmgr_sec_cm_testplan.hjson"]
+
+   testpoints: [
+
+diff --git a/dv/rstmgr_sim_cfg.hjson.tpl b/dv/rstmgr_sim_cfg.hjson.tpl
+index b12e73a..3c50439 100644
+--- a/dv/rstmgr_sim_cfg.hjson.tpl
++++ b/dv/rstmgr_sim_cfg.hjson.tpl
+@@ -12,7 +12,7 @@
+   tb: tb
+
+   // Simulator used to sign off this block
+-  tool: vcs
++  tool: xcelium
+
+   // Fusesoc core file used for building the file list.
+   fusesoc_core: ${instance_vlnv("lowrisc:dv:rstmgr_sim:0.1")}
+@@ -25,16 +25,16 @@
+
+   // Import additional common sim cfg files.
+   import_cfgs: [// Project wide common sim cfg file
+-                "{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson",
++                "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/common_sim_cfg.hjson",
+                 // Common CIP test lists
+-                "{proj_root}/hw/dv/tools/dvsim/tests/csr_tests.hjson",
+-                "{proj_root}/hw/dv/tools/dvsim/tests/alert_test.hjson",
+-                "{proj_root}/hw/dv/tools/dvsim/tests/tl_access_tests.hjson",
+-                "{proj_root}/hw/dv/tools/dvsim/tests/sec_cm_tests.hjson",
++                "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/csr_tests.hjson",
++                "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/alert_test.hjson",
++                "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/tl_access_tests.hjson",
++                "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/sec_cm_tests.hjson",
+                 // Just run the stress_all sequence, and don't inject random
+                 // resets since we may get overlapping resets due to sequences
+                 // that inject them.
+-                "{proj_root}/hw/dv/tools/dvsim/tests/stress_all_test.hjson"
++                "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/stress_all_test.hjson"
+                 ]
+
+   // Specific exclusion files.
+diff --git a/dv/rstmgr_cnsty_chk/rstmgr_cnsty_chk_sim_cfg.hjson.tpl b/dv/rstmgr_cnsty_chk/rstmgr_cnsty_chk_sim_cfg.hjson.tpl
+index 42f8b22..1107fe8 100644
+--- a/dv/rstmgr_cnsty_chk/rstmgr_cnsty_chk_sim_cfg.hjson.tpl
++++ b/dv/rstmgr_cnsty_chk/rstmgr_cnsty_chk_sim_cfg.hjson.tpl
+@@ -21,7 +21,7 @@
+   testplan: "{self_dir}/data/rstmgr_cnsty_chk_testplan.hjson"
+
+   // Import additional common sim cfg files.
+-  import_cfgs: ["{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson"]
++  import_cfgs: ["{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/common_sim_cfg.hjson"]
+
+
+   // Specific exclusion files.
diff --git a/hw/vendor/patches/lowrisc_ip/rstmgr/0002_Fix_Templates.patch b/hw/vendor/patches/lowrisc_ip/rstmgr/0002_Fix_Templates.patch
new file mode 100644
index 000000000..5ceb77777
--- /dev/null
+++ b/hw/vendor/patches/lowrisc_ip/rstmgr/0002_Fix_Templates.patch
@@ -0,0 +1,86 @@
+diff --git a/dv/env/rstmgr_if.sv.tpl b/dv/env/rstmgr_if.sv.tpl
+index cb2102d..25c6fe2 100644
+--- a/dv/env/rstmgr_if.sv.tpl
++++ b/dv/env/rstmgr_if.sv.tpl
+@@ -13,7 +13,7 @@ elif "io" in all_clks:
+ else:
+     assert 0, "No preferred clock available"
+ 
+-preferred_rst_n = f"rst_lc_{preferred_domain}_n"
++preferred_rst_n = f"rst_{preferred_domain}_n"
+ %>\
+ 
+ interface rstmgr_if (
+diff --git a/dv/env/seq_lib/rstmgr_reset_vseq.sv.tpl b/dv/env/seq_lib/rstmgr_reset_vseq.sv.tpl
+index 356807f..1670853 100644
+--- a/dv/env/seq_lib/rstmgr_reset_vseq.sv.tpl
++++ b/dv/env/seq_lib/rstmgr_reset_vseq.sv.tpl
+@@ -127,8 +127,8 @@ class rstmgr_reset_vseq extends rstmgr_base_vseq;
+     expected_cpu_enable = 0;
+ 
+     cfg.clk_rst_vif.wait_clks(8);
+-    // Wait till rst_lc_n is inactive for non-aon.
+-    `DV_WAIT(cfg.rstmgr_vif.resets_o.rst_lc_n[1])
++    // Wait till rst_io_n is inactive for non-aon.
++    `DV_WAIT(cfg.rstmgr_vif.resets_o.rst_io_n[1])
+ 
+     check_reset_info(get_reset_code(start_reset, 0), {reset_name[start_reset], " reset"});
+     check_alert_info_after_reset(expected_alert_dump, expected_alert_enable);
+@@ -184,7 +184,7 @@ class rstmgr_reset_vseq extends rstmgr_base_vseq;
+       reset_done();
+ 
+       cfg.${preferred_clk_rst_vif}.wait_clks(8);
+-      wait(cfg.rstmgr_vif.resets_o.rst_lc_n[1]);
++      wait(cfg.rstmgr_vif.resets_o.rst_io_n[1]);
+       check_reset_info(expected_reset_info_code);
+       check_alert_info_after_reset(.alert_dump(expected_alert_dump),
+                                    .enable(expected_alert_enable));
+diff --git a/dv/sva/rstmgr_cascading_sva_if.sv.tpl b/dv/sva/rstmgr_cascading_sva_if.sv.tpl
+index 143d0ed..1653cb6 100644
+--- a/dv/sva/rstmgr_cascading_sva_if.sv.tpl
++++ b/dv/sva/rstmgr_cascading_sva_if.sv.tpl
+@@ -183,17 +183,21 @@ interface rstmgr_cascading_sva_if (
+                     resets_o.rst_por_${clk + "_" if clk != "main" else ""}n[rstmgr_pkg::DomainAonSel], SyncCycles, clk_${clk}_i)
+ % endfor
+ 
+-  // Controlled by rst_lc_src_n.
+-  `CASCADED_ASSERTS(CascadeLcToLcAon, rst_lc_src_n[rstmgr_pkg::DomainAonSel],
+-                    resets_o.rst_lc_aon_n[rstmgr_pkg::DomainAonSel], SysCycles, clk_aon_i)
+-  `CASCADED_ASSERTS(CascadeLcToLc, rst_lc_src_n[rstmgr_pkg::DomainMainSel],
+-                    resets_o.rst_lc_n[rstmgr_pkg::DomainMainSel], SysCycles, clk_main_i)
+-
+   // Controlled by rst_sys_src_n.
+-  `CASCADED_ASSERTS(CascadeSysToSys, rst_sys_src_n[rstmgr_pkg::DomainMainSel],
+-                    resets_o.rst_sys_n[rstmgr_pkg::DomainMainSel], PeriCycles, clk_main_i)
+-  `CASCADED_ASSERTS(CascadeLcToLcShadowed, rst_lc_src_n[rstmgr_pkg::DomainMainSel],
+-                    resets_o.rst_lc_shadowed_n[rstmgr_pkg::DomainMainSel], SysCycles, clk_main_i)
++  `CASCADED_ASSERTS(CascadeSysToMain_A, rst_sys_src_n[rstmgr_pkg::DomainMainSel],
++                    resets_o.rst_main_n[rstmgr_pkg::DomainMainSel], PeriCycles, clk_main_i)
++
++  `CASCADED_ASSERTS(CascadeSysToIO_A, rst_sys_src_n[rstmgr_pkg::DomainMainSel],
++                    resets_o.rst_io_n[rstmgr_pkg::DomainMainSel], PeriCycles, clk_io_i)
++
++  `CASCADED_ASSERTS(CascadeSysToSPIHost_A, rst_sys_src_n[rstmgr_pkg::DomainMainSel],
++                    resets_o.rst_spi_host_n[rstmgr_pkg::DomainMainSel], PeriCycles, clk_io_i)
++
++  `CASCADED_ASSERTS(CascadeSysToSPIDevice_A, rst_sys_src_n[rstmgr_pkg::DomainMainSel],
++                    resets_o.rst_spi_device_n[rstmgr_pkg::DomainMainSel], PeriCycles, clk_io_i)
++
++  `CASCADED_ASSERTS(CascadeSysToI2C_A, rst_sys_src_n[rstmgr_pkg::DomainMainSel],
++                    resets_o.rst_i2c_n[rstmgr_pkg::DomainMainSel], PeriCycles, clk_io_i)
+ 
+   `undef FALL_ASSERT
+   `undef RISE_ASSERTS
+diff --git a/dv/tb.sv.tpl b/dv/tb.sv.tpl
+index c2e8ce4..49dbb57 100644
+--- a/dv/tb.sv.tpl
++++ b/dv/tb.sv.tpl
+@@ -12,7 +12,7 @@ elif "io" in all_clks:
+ else:
+     assert 0, "No preferred clock available"
+ 
+-preferred_rst_n = f"rst_lc_{preferred_domain}_n"
++preferred_rst_n = f"rst_{preferred_domain}_n"
+ preferred_por_n = f"rst_por_{preferred_domain}_n"
+ %>\
+ module tb;