Design new Ethernet framing top

[raylau1]

The Ethernet framing top is an AXI4 device which converts the AXI-Stream packet interfaces from a vendor Ethernet MAC core to a memory-mapped bus interface. It allows a host to send and receive MAC layer packets by reading or writing CSRs, transmit buffers and receive buffers.

This issue contains a draft specification for a new framing top which will replace the existing framing top from the ariane-ethernet repository.

Draft specification

Registers

Register Name	Offset	Length (Bytes)	Description
INTR_STATE	0x0	4	Interrupt State Register
INTR_ENABLE	0x4	4	Interrupt Enable Register
INTR_TEST	0x8	4	Interrupt Test Register
-	0xc	4	-
CTRL	0x10	4	MAC Control Register
STATUS	0x14	4	MAC Status Register
MACLO	0x18	4	Lower MAC Address Register
MACHI	0x1C	4	Upper MAC Address Register
TX_CTRL	0x20	4	Transmit Control Register
RX_BUFFER_FIFO	0x24	4	Receive buffer FIFO Front
RX_BUFFER_POP	0x28	4	Receive buffer FIFO Pop
MDIO_CTRL	0x2C	4	MDIO Control Register
RPLR0	0x30	4	Receive buffer 0 packet length
RPLR1	0x34	4	Receive buffer 1 packet length
RPLR2	0x38	4	Receive buffer 2 packet length
RPLR3	0x3C	4	Receive buffer 3 packet length
RPLR4	0x40	4	Receive buffer 4 packet length
RPLR5	0x44	4	Receive buffer 5 packet length
RPLR6	0x48	4	Receive buffer 6 packet length
RPLR7	0x4C	4	Receive buffer 7 packet length

Buffers

Register Name	Offset	Length (Bytes)	Description
TX_BUFFER	0x1000	2048	Transmit buffer
RX_BUFFER0	0x4000	2048	Receive buffer 0
RX_BUFFER1	0x4800	2048	Receive buffer 1
RX_BUFFER2	0x5000	2048	Receive buffer 2
RX_BUFFER3	0x5800	2048	Receive buffer 3
RX_BUFFER4	0x6000	2048	Receive buffer 4
RX_BUFFER5	0x6800	2048	Receive buffer 5
RX_BUFFER6	0x7000	2048	Receive buffer 6
RX_BUFFER7	0x7800	2048	Receive buffer 7

Register fields

INTR_STATE

Bits	Type	Reset	Name	Description
31:1				Reserved
0	rw1c	0x0	rx_avail	Received packet available.

INTR_ENABLE

Bits	Type	Reset	Name	Description
31:1				Reserved
0	rw	0x0	rx_avail	Enable interrupt when a received packet is available.

INTR_TEST

Bits	Type	Reset	Name	Description
31:1				Reserved
0	wo	0x0	rx_avail	Write 1 to force INTR_STATE.rx_avail to 1.

CTRL

Bits	Type	Reset	Name	Description
31:1				Reserved
0	rw	0x0	promiscuous	Promiscuous mode enable.

STATUS

Bits	Type	Reset	Name	Description
31:2				Reserved
1	ro	0x0	rx_avail	Received packet available.
0	ro	0x0	tx_busy	Transmit busy.

MACLO

Bits	Type	Reset	Name	Description
31:0	rw	0x0	mac_low	MAC address lower 32-bits.

MACHI

Bits	Type	Reset	Name	Description
31:16				Reserved
15:0	rw	0x0	mac_high	MAC address upper 16-bits.

TX_CTRL

Bits	Type	Reset	Name	Description
31:11				Reserved
10:0	rw	0x0	tx_packet_len	Tx packet length (bytes). Write to transmit packet.

RX_BUFFER_FIFO

Bits	Type	Reset	Name	Description
31	ro	0x0	rx_buffer_valid	FIFO front is valid.
30:3				Reserved
2:0	ro	0x0	rx_buffer	Rx buffer containing the next received packet. Reading this does not pop from the FIFO.

RX_BUFFER_POP

Bits	Type	Reset	Name	Description
31:1				Reserved
0	wo	0x0	rx_buffer_pop	Pop the front entry in the Rx buffer FIFO.

MDIO_CTRL

Bits	Type	Reset	Name	Description
31:4				Reserved
3	ro	N/A	mdio_i	MDIO input.
2	rw	0x0	mdio_oen	MDIO output enable.
1	rw	0x0	mdio_o	MDIO output.
0	rw	0x0	mdio_clk	MDIO clock.

RPLRx

Bits	Type	Reset	Name	Description
31:11				Reserved
10:0	ro	0x0	len	Packet length (bytes).

Software flow

Transmit packet (alternative 1)

1. Write data to TX_BUFFER
2. Write packet length (bytes, not including FCS) to TX_CTRL and begin transmitting packet.
3. Poll STATUS until tx_busy is 0.

Transmit packet (alternative 2)

1. Poll STATUS until tx_busy is 0.
2. Write data to TX_BUFFER
3. Write packet length (bytes, not including FCS) to TX_CTRL and begin transmitting packet.

Receive packet

1. Wait for interrupt or poll STATUS until rx_avail is 1.
2. Read RX_BUFFER_FIFO to get the buffer index containing the received packet.
3. Use buffer index to read RPLRx to get the packet length.
4. Use buffer index to read RX_BUFFERx to get the packet data.
5. Write 1 to RX_BUFFER_POP to free the Rx buffer
6. Clear interrupt by writing to INTR_STATE is necessary.

Reference block diagram