Issues

• [eudsl-llvmpy] MIR: run codegen to a named pass and retain the MIR for inspection (e.g. post-RA)

  llvm/eudsl#653 · Filter by author makslevental opened on Aug 27, 2026

• Re-do MLIR Python bindings hand-written over the C++ API (the eudsl-llvmpy way)

  llvm/eudsl#651 · Filter by author makslevental opened on Aug 27, 2026

• [eudsl-llvmpy] MIR: allow multiple MachineFunctions in one hand-built module (create_machine_function makes exactly one)

  llvm/eudsl#645 · Filter by author makslevental opened on Aug 26, 2026

• [eudsl-llvmpy] Add an MCP server (persistent LLVM Python REPL), modeled on mlir-python-mcp

  enhancement
  llvm/eudsl#616 · Filter by author makslevental opened on Aug 24, 2026

• [eudsl-llvmpy] Design: a canonical live-value registry (dedup + identity + invalidation) for Value/Instruction/BasicBlock wrappers

  llvm/eudsl#615 · Filter by author makslevental opened on Aug 24, 2026

• [eudsl-llvmpy] Free-threaded data races in unsynchronized static registries (casterMap + Python-pass registries)

  llvm/eudsl#614 · Filter by author makslevental opened on Aug 24, 2026
  1

• [eudsl-llvmpy] Python-driven register allocators and instruction schedulers (MIR codegen)

  enhancement
  llvm/eudsl#600 · Filter by author makslevental opened on Aug 23, 2026
  1

  

• [design] Lowering hand-built generic MIR (Route A) blocked by GlobalISel/SelectionDAG entry-point tension

  enhancementquestion
  llvm/eudsl#594 · Filter by author makslevental opened on Aug 19, 2026
  2

• [TODO] migrate ArithValue to use cmp enums themselves instead of strings.

  enhancementgood first issuetodo
  llvm/eudsl#230 · Filter by author makslevental opened on Nov 19, 2025
  1