Greetings!
I have encountered two minor issues in your project:
- File
ja_bits_out.v has .v extension but this file does not contain Verilog code. This is a bit confusing.
- In file
cr_huff.v you have inconsistency with IEEE-1364-2005 (output output_reg_count has to be declared with the same range as it is declared later, that is [4:0]: output [4:0] output_reg_count ). Quote (clause 12.3.3): "If a port declaration does not include a net or variable type, then the port can be again declared in a net or variable declaration. If the net or variable is declared as a vector, the range specification between the two declarations of a port shall be identical. Once a name is used in a port declaration, it shall not be declared again in another port declaration or in a data type declaration."
Greetings!
I have encountered two minor issues in your project:
ja_bits_out.vhas.vextension but this file does not containVerilogcode. This is a bit confusing.cr_huff.vyou have inconsistency with IEEE-1364-2005 (output output_reg_counthas to be declared with the same range as it is declared later, that is [4:0]:output [4:0] output_reg_count). Quote (clause 12.3.3): "If a port declaration does not include a net or variable type, then the port can be again declared in a net or variable declaration. If the net or variable is declared as a vector, the range specification between the two declarations of a port shall be identical. Once a name is used in a port declaration, it shall not be declared again in another port declaration or in a data type declaration."