From 102eaf633644573facc2f6896b3ba2ef5997c680 Mon Sep 17 00:00:00 2001 From: Pablo Collado Soto Date: Thu, 23 Jul 2026 09:34:45 +0200 Subject: [PATCH] fix: account for primed bytes Data primed into the UART TX FIFO must be tracked not only for indexing the remaining data, but also for returning the amount of written bytes so that `writeAll` can terminate. --- port/raspberrypi/rp2xxx/src/hal/uart.zig | 1 + 1 file changed, 1 insertion(+) diff --git a/port/raspberrypi/rp2xxx/src/hal/uart.zig b/port/raspberrypi/rp2xxx/src/hal/uart.zig index a175e71e7..891ad363d 100644 --- a/port/raspberrypi/rp2xxx/src/hal/uart.zig +++ b/port/raspberrypi/rp2xxx/src/hal/uart.zig @@ -368,6 +368,7 @@ pub const UART = enum(u1) { var iter = microzig.utilities.SliceVector([]const u8).init(payloads).iterator(); while (iter.next_chunk(null)) |payload| { var offset: usize = uart.prime_tx_fifo(payload); + written += offset; while (offset < payload.len) { while (!uart.is_writeable()) { try deadline.check(time.get_time_since_boot());