Hi, all!
Using static analysis methods there are some dead transitions was found in FSM presented in ct_ciu_snb_sab_entry.v rtl model file.
here is local wire which assigned to 0 and never redefined or passed into any instance as output. But it checked in some if conditions in FSM (for example here and here which is always false. So, some FSM transitions to MEMR are dead by default.
Is this a bug or was it done this way on purpose?
Hi, all!
Using static analysis methods there are some dead transitions was found in FSM presented in ct_ciu_snb_sab_entry.v rtl model file.
here is local wire which assigned to
0and never redefined or passed into any instance as output. But it checked in some if conditions in FSM (for example here and here which is always false. So, some FSM transitions toMEMRare dead by default.Is this a bug or was it done this way on purpose?